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High-speed digital IC package characterization,
using microwave probing and fixturing techniques
Arthur Fraser
Cascade Microtech, Inc.
Beaverton, Ore.
Introduction
Digital VLSI packages are now required to operate at clock rates of 50-250 MHz and beyond. This requires analog bandwidths of 500 to 2500 MHz for good edge definition (see Appendix A for a discussion of how analog bandwidth relates to digital bandwidth). At these frequencies, typical digital packages will exhibit electrical behavior completely unpredicted from low frequency measurements and models. Complicating the issue, typical digital packages have metal pattern dimensions that resonate, and/or couple to the outside environment-they can act as antennas and resonators. This is the microwave region, where open lines may appear as short circuits and shorted lines as opens, depending on the frequency. Microwave designers have been successfully working with these issues for years, and now these techniques need to be adapted to the high-speed digital design environment.
The focus of this paper is to demonstrate techniques to fixture and accurately measure the high-frequency characteristics of digital IC packages. Microwave wafer probes are used to accurately measure a 169-pin PGA through the use of a special interface fixture that adapts the package to microwave probe requirements. The interface fixture is designed to duplicate the ECB environment the package will be mounted in, because the ECB has an effect on high frequency performance.
All package measurements are aimed at developing an accurate package model which a designer can use with confidence. This requires accurate measurements and a frequency limit (beyond the limit the model is not valid). The implication is that packages must be measured well beyond the maximum frequency of interest, so as to demonstrate at what frequency the model is valid.
Tom Strouth
Gigatest Labs
Cupertino, Calif.
Background
Digital IC designers and IC-package designers are now encountering high-frequency package limitations. These limitations typically appear as one of the following problems, after the IC has been designed and packaged:
a. Ground bounce (common-ground inductance) b. Crosstalk (common-ground inductance and capacitive/inductive coupling between signal traces) c. Power supply decoupling (series inductive elements in decoupling components and in supply lines)
Ground bounce is currently the biggest electrical problem in the silicon digital packaging industry. This is because it is often assumed that “ground” is everywhere at a constant zero volt potential. This not true in the real world. Ground bounce is caused by an inductance in the ground return path of the package¹ (fig. 1). The voltage drop across where i is the current flowing through will resonate with parasitic capacitance resulting in a typical damped second-order response shown in figure 2 (the assumption is that the output driver turns on faster than the ringing frequency of the LC circuit). This results in risetime degradations and failure to meet VOH and VOL timing specifications when the IC is mounted in the package.
An additional problem related to the ground inductance is that is common to all circuits on the IC (in this example). Whatever voltage drop appears across due to one or more outputs switching, will affect all other circuits on the IC. So all VOLs will be compromised and all input noise margins, for example, will be adversely affected. In microwave circuits, this is simply another form of crosstalk and is modeled by including all ground inductances.
Figure 1 Simplified ground bounce model.^ is the package common-around inductance.
Figure 2 Degradation of rise and fall times due to common-ground inductance. Resonance of with parasitic capacitance causes ringing.
Figure 3 package.
First-order equivalent circuit of a digital IC
Most digital engineers are familiar with using time-domain reflectometry (TDR) data. It is easy to interpret because it directly relates to physical dimensions, and preliminary models are easy to “pull of the screen.” There are, however, two basic problems with TDR. One is that there is currently no quantitative way to use TDR data to optimize a model, so that the resultant hand-optimized models are more qualitative than quantitative. Secondly, until now there has been no accurate way to repeatably connect the TDR to the package under test.
A variety of fixtures have been constructed to connect TDRs to various structures, but all generally have poor repeatability.^7 Current TDRs, such as the HP 54120, can calibrate out the effects of a fixture, but the calibration is only as good as the repeatability of the fixture. Additionally, the problem is even worse because several standards must be contacted, with uncertain repeatability each time. If the fixture repeatability is 10% (a typical number), then this error is now included as part of the calibration constants. Depending on the direction of the errors during calibration, the subsequent measurements could be as much as 20% in error. The use of microwave probes to overcome this problem is discussed in the paper by Carlton, D. E., et al, “Accurate measurement of high-speed package and interconnect parasitics."
Accurate high-frequency equipment and fix-bring for package characterization
High-frequency equipment for measuring small structures is readily available. A typical equipment list:
l Microwave probe station Cascade Microtech Summit 9000™ Analytical Probe Station
l Coplanar probes Cascade Microtech WPH series
l Package interface to microwave probes
PASlFx board, GigaTest Labs
l Network analyzer, TDR HP 85106
l Surrogate Chip and misc. cables
Cascade Microtech
These measurement systems are comprised of mature test technology, with well understood and traceable accuracy. The PASlFx board and Surrogate Chip’” test substrate are the new pieces which adapt this measurement system for package measurements.
Ultra-high frequency wafer probes (fig. 4) were developed by Cascade Microtech seven years ago for quickly assessing how process changes would affect GaAs FET parameters. Cascade Microtech now offers probes through 75 GHz. Because these probes are much more precisely made than fixtures and can be positioned with 1-2 micron accuracy, they offer repeatability of 0.1% (- dB) through 10 GHz, compared with 10% repeatability for fixtures. This level of repeatability is necessary to develop accurate models, otherwise the resultant model will inadvertently include the fixture errors, in addition to the desired model.
When used with automatic network analyzers (HP 8510 for example), and TDRs such as the HP 54120, the probe response can be calibrated out by using the Cascade Microtech impedance standard substrate (ISS) shown in figure 5. This substrate contains various precision elements (0.1% resistors, transmission lines, shorts, through-connections, etc.) that are necessary to calibrate the measurement system up to the probe tips. After calibration the measurement system will measure only what is beyond the probe tips. In microwave terms, the reference plane is set at the probe tips,
The GigaTest Labs Package Adapter Socket Interface Fixture (PASIFx) was developed to allow the user to easily and quickly use microwave wafer probes to contact virtually any package for electrical measurements. The PASlFx board is shown in figures 6 and 7. The board is designed for a 169-pin PGA, and has the same characteristics as the board in which the package will be used-same thickness, same material, same plating process, and same design rules. The adapter must have the same characteristics as the board because at high frequencies the package and the board may interact, and this interaction will be included in the measurements, Additionally, for packages with multiple ground pins with no internal planes, these pins need to be connected together.
The Cascade Microtech Surrogate Chip is used to furnish an internal “standard termination” for the package. These components are a new group of products designed to assist package measurements. Each Surrogate Chip has an array of test reference plane adjusters, and also has calibration elements on each chip. For this application, this thin-film chip is used to replicate a linear load of the package signal traces on the inside of the package. A Surrogate Chip photo is shown in figure 31.
Figure 4 probes.
Details of Cascade Microtech coplanar wafer
Figure 5 (^) Cascade Microtech Impedance Standard Substrate contains precision calibration standards for use through 75 GHz.
Figure 6 (^) GigaTest Labs PASlFx board with 169-pin PGA package.
Figure 9 169-pin PGA package used for measurements.
Figure 10 Details of fixture and package probing.
The probes, in this case, each have two contacts (signal and ground), with center-to-center spacing of 400 Contact is made to the center land and the adjacent fixture-ground plane, as shown in figure 11. With the PASlFx board, and by making the proper connections on the board and within the cavity, all measurements necessary to completely characterize the package can be easily made.
Figure 11 Details of probes contacting the lands on the PASlFx board.
Experimental results The experimental results include data from two measurement activities. The test measurement system was first verified by using known physical and electrical structures. After verification, the previously described example was measured.
Verification measurements Measurements were first made on a fixture verification board (fig. 12) to verify the basic concept of high-frequency measurements on circuit board material. The verification board contains shorted and open 50-ohm microstrip transmission lines of various lengths, which were measured using the previously described equipment, shown in figure 13. The equipment used is listed in the previous section.
Care was taken to minimize external reflections by placing RF absorber material (Eccosorb™) on the chuck face and by using the same material to space the verification board about 3/8 inch above the chuck. Two calibrations were performed, a calibration from 0.05-10 GHz for the analog measurements and a 0.0520 GHz calibration for the TDR measurements. The wider bandwidth calibration was used with the TDR to obtain higher spatial resolution.
The calibrations were performed by first loading the calibration constants into the HP 8510, using a predefined calibration tape, and then sequentially contacting the calibration patterns on the impedance standard substrate, as shown in figure 14. This calibration typically takes five minutes, and with a warmed-up and stabilized system, will typically be valid for a week.
The S-parameters of the longest transmission line are shown in figure 15. The loss through the transmission line is a function of frequency, and this represents good performance. For this measurement the adjacent lines were terminated to ground with 50-ohm resistors. If this was not done, little dips (1-2 dB) in the response would be present due to adjacent-line resonance. Note that both power dB and voltage ratio scales are provided. Energy reflected to the port 1 probe, is a function of line deviation from 50 ohms, discontinuities on the line (such as through holes at each end), and coupling to adjacent lines. The performance, again, is good. This data indicates that good performance (through 10 GHz) 50-ohm microstrip transmission lines have been fabricated on FR circuit board material.
1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 0 1 2 3 4 5 6
Figure 12 Top view of fixture verification board, showing open and shorted transmission lines.
Figure 13 Typical equipment setup, with an HP 8510 network analyzer and Cascade Microtech Summit 9000™ analytical probe station.
Another measurement of interest is the cross coupling between two adjacent lands on the PASlFx board (fig. 7). The data, shown in figure 18, demonstrates that cross coupling is a monotonic function of frequency and is sufficiently low through 4 GHz so that it will not mask actual package crosstalk measurements. (The PASlFx board lands can be redesigned to additionally minimize cross coupling.) A general guideline: adjacent-line crosstalk of most digital IC packages, at the maximum-rated frequency, is usually greater than -30 dB (3%) and is often greater than -10 dB (30%).
2.00 4.00 6.00 6.00 10. Frequency [GHz] Figure 18 Cross coupling between adjacent lands on PASlFx board with no package installed.
The conclusion of these measurements is that this fixture, as designed and fabricated, will function for accurate package measurements through at least 4 GHz. If additional bandwidth is desired, then fixture lands could be modified to reduce cross coupling to adjacent lands, and a 10 GHz bandwidth is likely.
The approach used to measure ground inductance was to (a) wire bond all VCC, VEE, VTT cavity traces to the cavity plane (the cavity plane is the VEE plane in this case); (b) connect all the package ground pins to the fixture plane except one (A8), resulting in the first-order equivalent circuit shown in figure 19. Thus, the inductance measured is primarily that of just one pin, and the effect of the other pins inductance is the same as pin A8. The measurements are shown on a Smith chart (fig. 20). Recall that on a Smith chart, all purely resistive values lie on the horizontal axis, with (in this case) 50 ohms in the center, 0 ohms on the far left, and infinite ohms on the far right. Inductive responses are on the top semicircle, and capacitive on the bottom. The frequency response of a pure inductor would start at the far left at dc (a short circuit), and as the frequency increased, would travel clockwise around the top of the Smith chart until finally, at infinite frequency, it would be at the far right point.
Package measurements Package description The package measurements were all made on a 169-pin PGA (fig. 9) designed at National Semiconductor for ECL use. This package is relatively sophisticated in design and has five planes; 3 VCC, 1 VTT, and 1 VEE planes. The two signal-trace planes are located between the three VCC planes, resulting in what is known in the microwave world as stripline. With this many planes it is expected the ground inductance will be small and most of the inductance will be contributed by the package leads. An additional benefit of using the three VCC planes is expected to be constant impedance signal traces. Constant-impedance traces have relatively low cross coupling between adjacent traces because the signal-trace electric fields will be terminated mostly to the
Figure 19 (^) Equivalent circuit of the VCC plane (ground) inductance measurement. All VCC pins are connected to fixture ground except A8, which is measured.
VCC planes, rather than intersecting adjacent signal traces. The pin labeling scheme is as shown in figure 7.
Equipment The equipment used is the same as for the verification measurements. The calibration ranges are also the same.
Common-ground inductance measurement The ground inductance is common to all measurements and is one of the most difficult parameters to measure accurately. It is recommended that the ground inductance be measured first, as it may be a significant part of all other measurements and inadvertent errors may result if the common-ground inductance is not considered.
Figure 20 Smith chart response of ground-inductance measurement. Note initial inductive response, followed by three closely spaced (in frequency) resonances (looping).
The S-parameter data (fig. 20) shows an inductive response up to 1.1 GHz, with a small resistive component (indicated by the response moving inside the Smith chart) then various resonances are encountered, indicated by the looping on the Smith chart. The inductance value is 4.5 nH, and since there are 15 VCC pins, the average VCC plane common inductance is 0.28 nH. One can also measure other VCC pins to see if there is a spatial dependence on the inductance value (if there is, then a more complex model may be required).
Open trace TDR The HP 8510 was used in the TDR mode (20 GHz bandwidth) to look at the longest and shortest signal traces and two signal traces in between (fig. 21). The signal traces were not terminated in the cavity. When the physical length is plotted versus the round-trip delay (fig. 22), all the points lie on a straight line, as expected. The Y-intercept is the trace end effect, and the length of the package pin connected to the PASlFx board. The TDR data indicates that the package signal traces are not 50 ohms, but rather about 30 ohms, and some signal traces are relatively constant impedance, whereas others are not. Note the response due to the capacitive load on the land and via of the PASlFx board, and the inductive response due to each package pin.
Figure 21 TDR of the longest, shortest, and two additional signal traces in the 169-pin PGA. The traces are not terminated in the cavity.
Figure 22 Plot of physical length versus round trip delay for the signal traces TDR’d in figure 21. The propagation velocity is the slope of the line, corrected to a one-path delay.
Figure 26 Photo showing Cascade Microtech Surrogate Chip terminating signal traces A1 and A2 for cross-coupling measurements.
Figure 27 Cross-coupling measurements between signal traces A1 and A2, terminated in cavity with 30 ohms.
Discussion of package measurements and preliminary modeling The Smith chart response of the ground inductance demonstrates a fundamental problem in package design. As shown in figure 20, the response below 1 GHz is inductive, with a slight resistive component, then at about 1.1 GHz a resonance occurs, followed immediately by two more resonances. The first resonance is probably caused by the VCC plane resonating. The first resonance point of a metal plane occurs at a half wavelength. From figure 22, the signal propagation velocity is 3.45 mils/ps, and the VCC planes are roughly 1.7 x 1.7 inches in size. Recall that
where 1 is the wavelength in units of time and f is the frequency.
In this case
= (1.75 inches)/3.45 ps/mil) = 0.5 ns
or f = 1 GHz
which corresponds very closely to the measured value of 1.1 GHz. The other two resonances may be the other two VCC planes, coupled by the inductive pins, which may tune the resonances slightly, or it may be the VTT and VEE planes resonated in sequence.
Recall that what is being measured in figure 20 and modeled in figure 28 is the inductance of basically one VCC pin, and the VCC plane resonance. Given that there are 15 VCC pins in this package, the resultant equivalent VCC plane inductance circuit is shown figure 29. This model is expected to be accurate through 1.1 GHz, the frequency at which the first resonance occurs. It will be a subject of a future paper to model this resonance. Note that when an actual die is placed in the cavity, bond wires will connect the VCC pads to the VCC traces, and the composite inductance of these bond wires should be added in series 0.5 Ohms
- 100 MHz Steps **Figure 28 Proposed initial model for VCC plane (ground) inductance measurement (a), up to the first resonance frequency, and the calculated response of this model (b). Compare with measurement in figure
- Note this is the model of one VCC pin and the VCC plane.**
Package Boundary
Figure 29 Proposed VCC plane (ground) inductance equivalent circuit, modeling up to the first resonance frequency. This model does not include the inductance, due to bond wires from die to VCC traces.
Ground plane resonance is a fundamental performance limit of a package. What occurs at resonance is that the plane is no longer equipotential, but rather is acting like an antenna, radiating to the dielectric, and to all signal traces on the package. Given that this resonance occurs at approximately 1 GHz, and using the analog to digital bandwidth rule of thumb of 10:1 this would imply a maximum clock rate for this package of 100 MHz, for ground plane resonance limitations only.
The transmission measurements of figures 23, 24, and 25 illustrate the problem of impedance mismatch. Looking at figure 25, the transmission response the transmission is fairly flat through 0.8 GHz, then drops to -10 dB (32%) at 1.5 GHz. At this same frequency
Figure 31 Surrogate Chip’” test substrates (patent pending) with calibration standards (top half) and short transmission lines where the probes land (bottom half). The short transmission lines are wire bonded to the traces to be measured, and to ground.
Conclusions Accurate characterization of current digital IC packages requires instrumentation with analog bandwidths of 5 GHz for frequency domain measurements, and 20 GHz for high spatial-resolution TDR measurements. Complete package characterization involves measuring and modeling:
l common ground impedance l cross coupling of the signal lines l power supply impedance l transmission loss of the signal lines
This paper has demonstrated:
- Highly accurate measurements of a complex digital IC package can be easily and quickly performed using Cascade Microtech microwave wafer probes, the PASlFx board to adapt packages to microwave probes, and a Hewlett- Packard 8510B network analyzer.
- Data obtained from these measurements can be used to optimize selected models, using various linear and nonlinear optimizing programs,
- Ground plane resonances were measured at 1.1 GHz and above. These resonances define a package upper frequency limit, which would not be detected by low-frequency measurement and modeling techniques.
References
- West, Jeffrey A. “Design guide for SPICE simulation of Signetics bipolar logic,” Signetics Orem Design Center, Orem, Utah, 1989.
- Bhattacharyya, D, et al, “Ground plane design parameters for CMOS VLSI multilayer packages,” Ninth Annual International Electronics Packaging Conference, San Diego, Calif., 1989, pp 659-666.
- Callahan, R. and Ewanich, J. “The use of CAD in advanced ceramic package designs,” Ninth Annual International Electronics Packaging Conference, San Diego, Calif., 1989, pp 678-685.
- Mirchandani, Sandeep, “Modeling IC packages in high speed digital applications,” Hewlett-Packard High Speed Digital Test Solutions Symposium, Feb. 6,7,8, 1990, Paper
- Sayre, Ed, P. “Applying advanced TDR and TDT techniques to IC package measurements,” Hewlett-Packard High Speed Digital Test Solutions Symposium, Feb. 6,7,8 1990, Paper 4.
6 Sen, Bidyut. “LCZ Characterization of IC Packages and Decoupling Networks”, Hewlett-Packard High Speed Digital Test Solutions Symposium, Feb. 6,7,8 1990, Paper
Dunleavy, L. P. and Katehi, P. B. “Repeatability issues for de-embedding microstrip discontinuity S-parameter measurements by the TSD technique,” 27th ARFTG Conference Digest, Spring 1986, pp. 85-99.
Carlton D. E., et al. “Accurate measurement of high-speed package and interconnect parasitics," IEEE 1988 CICC, 23.3.1-23.3.7.
Cascade Microtech WPH-300 specification sheet.
Acknowledgements The authors wish to thank Sandeep Mirchandani of National Semiconductor for the packages used in this paper and for promoting the package characterization activity along with Dave Bellandi of Hewlett-Packard. The authors also with to thank Jerry Schappacher, Reed Gleason, and Keith Jones for their many suggestions.
Appendix A
Bandwidth requirements
A common question when measuring packaging is “how high in frequency should I measure my package to assure a required digital performance?” The most direct approach is to compute the Fourier expansion coefficients for a train of square waves and look at how each additional harmonic affects the risetime (fig. Al). This data can be linearly scaled for any arbitrary clock frequency as shown in figure A2. Note the assumptions here are (a) there is a symmetrical square-wave clock and (b) no phase shift as a function of frequency. In general, the expected risetime for a 100 MHz clock is about 0.5 ns, meaning that harmonic content to at least 900 MHz is required, and harmonic content to 1500 MHz would be desirable for a well-defined edge.
Figure A1 Risetime vs. harmonic content for a 100 MHz square wave.
