Higher Priority Task - Embedded Systems Application Programming - Past Exam Paper, Exams of Computer Programming

Main points of this exam paper are: Shared-Data, Ostrich Algorithm, Deadlock, Priority Inversions, Functional Queueing, Resource, Low Priority Task, Higher Priority Task, Chmod, Tail

Typology: Exams

2012/2013

Uploaded on 03/25/2013

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EE324 Embedded Systems Application Programming Page 1 of 8
Spring Examinations 2011-2012
Exam Code(s)
3BP1
Exam(s)
Third Year Electronic & Computer Engineering
Module Code(s)
EE324
Module(s)
Embedded Systems Applications Programming
Paper No.
Repeat Paper
External Examiner(s)
Professor G.W. Irwin
Internal Examiner(s)
Prof. G. ร“ Laighin
Dr. P. Corcoran
Instructions:
SECTION A: Answer question one (30 marks - attempt all questions)
and
SECTION B: Any two other questions (20 marks each) from the
remaining questions
2 hrs
8
Electrical & Electronic Engineering
Requirements:
MCQ
Handout
Statistical Tables
Graph Paper
Log Graph Paper
Other Material
pf3
pf4
pf5
pf8

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Spring Examinations 201 1 - 2012 Exam Code(s) 3BP Exam(s) Third Year Electronic & Computer Engineering Module Code(s) EE Module(s) Embedded Systems Applications Programming Paper No. Repeat Paper External Examiner(s) Professor G.W. Irwin Internal Examiner(s) Prof. G. ร“ Laighin Dr. P. Corcoran Instructions: SECTION A: Answer question one (30 marks - attempt all questions) and SECTION B: Any two other questions (20 marks each) from the remaining questions Duration: 2 hrs No. of Pages 8 Department(s) Electrical & Electronic Engineering Course Co-ordinator(s) Requirements : MCQ Handout Statistical Tables Graph Paper Log Graph Paper Other Material

SECTION A

**This section is compulsory; attempt all questions โ€“ 2 marks per question (total 30 marks)


Question A1.** A low priority task holds a resource needed by a higher priority task; this leads to a system state of? (a) shared-data; (b) the ostrich algorithm; (c) deadlock; (d) priority inversions; (e) functional queueing; (f) none of these Question A2. Which of the following commands is used to change file permissions on a POSIX compatible OS? (a) tail; (b) chmod; (c) cat; (d) man; (e) tr; (f) none of these Question A3. In an RTOS which of the following can not be used for inter-task communication? (a) task info block; (b) a semaphore; (c) mailbox; (d) queue; (e) a pipe; (f) none of these Question A4. Which of the following is NOT suitable as a software-architecture for an embedded system? (a) RTOS; (b) functional queueing; (c) round robin; (d) round robin + interrupts; (e) interrupt handlers; (f) none of these Question A5. Which of the following commands is used to provide a file listing of a directory on a POSIX compatible OS? (a) ps; (b) ls; (c) push; (d) sh; (e) grep; (f) none of these Question A6. Which of the following commands is used to find documentation on a POSIX compatible OS? (a) tail; (b) chmod; (c) cat; (d) man; (e) tr; (f) none of these Question A7. On what timescale should user interface (UI) components of an application respond to input? (a) 100 microsecond; (b) 10 millisecond; (c) 1 second; (d) 1 minute; (e) 1 hour; (f) none of these Question A8. Which of the following commands is used to list lines at the end of a file on a POSIX compatible OS? (a) tail; (b) chmod; (c) cat; (d) man; (e) tr; (f) none of these

SECTION B - Attempt TWO of four questions โ€“ 20 marks per question. ( NB: Candidates should note that marks may be lost if answers are not presented in a neat and orderly manner) ____________________________________________________ Q 1. (a) What are the 4 principle categories of software architecture employed in embedded systems? Explain the basic functionality of each with outline sketches or code segments to illustrate your answer. Compare each of these architectures under the headings of (i) availability of priority levels, (ii) worst-case response times, (iii) stability of response with code changes and (iv) simplicity. [6 marks] (b) In Fig 1 below the outline components of a basic solar heating system are shown. You are commissioned to design a system for a large villa which will incorporate 6 sets of solar collectors. Each has a water temperature sensor and a control valve. Temperatures in the collectors and the immersion tank should not exceed limits of T1 and T2. In addition to the immersion tank there is a heat-exchanger in the swimming pool of the villa and a bypass valve which can switch the water flow between immersion tank and swimming pool in case the immersion temperature is too high. (i) What are the most high-priority events in this system? (ii) What is the ballpark response time required from such a system? (iii) How many priority levels are needed? What user interface is required? [7 marks] (c) Decide on a suitable software architecture and hardware platform to implement such a system. Justify your decisions and discuss any additional system components that should be incorporated to ensure the system can operate reliably on a 24/7 basis. Provide a pseudo-code description of the main program loop, including (i) start-up check; (ii) hardware initialization; (iii) software initialization of all resources; (iv) task initializations (if any!); (v) start main tasks (if any!) and , finally, (vi) start main control loop or RTOS. Fig 1: Solar Heating Control System [7 marks] ____________________________________________________

Q 2. (a) Explain the shared-data problem which occurs between the application code and the interrupt handling code of an embedded system. Fig 2 shows some C-code which is susceptible to the shared-data problem. Explain how this code is intended to function and explain how intermittent errors can occur. [5 marks] Fig 2: Code to implement the reading of sensor data using interrupts. An alarm is triggered if both sensors do not have the same data reading. (b) Describe in detail three distinct algorithmic methods which can offer a solution to the shared data problem. Note briefly the advantages/disadvantages of each. Illustrate your discussion with example source code, flow charts, or diagrams, where appropriate. [10 marks] (c) Explain and differentiate between (i) interrupt latency, (ii) interrupt response, and (iii) interrupt recovery times. How will interrupt nesting affect these timings? Use diagrams and pseudo code examples as appropriate. **[5 marks]


Q 3. (a)** Explain what is meant by deadlock? Give an example of how it can occur. Suggest some approaches to avoid or mitigate the effects of this phenomenon. [3 marks] (b) In the context of an RTOS explain, using diagrams and/or code segments where appropriate, what is meant by: (i) a task; (ii) a semaphore; (iii) a task control block and (iv) a pipe. [4 marks] (c) Given task resource usage and availability as described in Table 3(b) below draw the resource allocation graph for this system. Using this resource allocation map determine (i) partially reduced and (ii) fully reduced resource allocation graphs. Is this system deadlocked? Is it unsafe? Explain how you arrived at these conclusions? [5 marks] (d) On a system using multi-level feedback queues a CPU-bound task requires 50ms to complete. The first queue uses a quantum of 5 ms and this is doubled for each lower-level queue. How many times will the job be interrupted and at what level queue will it terminate? [2 marks] static int iTemperatures[2]; void interrupt vReadTemperatures (void) { iTemperatures[0] = !! read in value from HW iTemperatures[1] = !! read in value from HW } void main (void) { int iTemp0, iTemp1; while (TRUE) { iTemp0 = iTemperatures[0]; iTemp1 = iTemperatures[1]; if (iTemp0 != iTemp1) !! Set off howling alarm; } }

(a) In one energy saving strategy the system switches immediately into the RUNNING mode (via UP state). After the task is executed it switches immediately (via DOWN state) to SLEEP mode. Now given that T = 200 ms sketch a graph of the state sequence and the power consumption in your answer book. (NB: example templates for these time graphs are given below.) [4 marks] (b) The system power supply is used with a 1.3 kJ battery. If the system is required to handle at least โ‚ฌ 5 ร— 106 task cycles what is the maximum cycle length, T, between tasks. And what is the maximum period in days that the system can operate from this battery? [3 marks] (c) In a second energy saving strategy the system switches immediately into the RUNNING mode as in (a), however it will only switch into SLEEP mode after exiting the RUNNING mode it there is at least 75 ms until the next task interrupt; if there is less than 75 ms it will remain in IDLE mode. Given that T=200 ms sketch a graph of the state sequence and the power consumption in your answer book. (NB: example templates for these time graphs are given below.) [4 marks] (d) Determine average energy consumption, E1, per cycle T for the strategy of section (a) and E the consumption of the strategy of section (c). What is the energy difference, E1 โ€“ E2, for T = 200 ms? [6 marks] (e) What is the minimum cycle time for the periodic task, T, if strategy E2 is to perform better than strategy E1? [3 marks] Fig 4(b): Graph template of CPU states transitions Vs time (ms) for the embedded system. Fig 4(c): Graph template of Power consumption Vs time (ms) for the embedded system. ____________________________________________________

EE321 Multi-Choice Question (MCQ) Answer Sheet

Mark each selection with a distinct โ€œXโ€. Include this sheet with main answer book. ( NB: where applicable you must include rough-work calculations to obtain full marks for these questions. Please write you name below, detach this sheet and include with you main exam answer-book.) Student Name: ___________________________ ID Number: ____________________

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