EE 231 Fall 2007
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Homework #4 Due October 17, 2007
7.1 Consider the timing diagram in Figure P7.1. Assuming that the D and Clock inputs
shown are applied to the circuit in Figure 7.12, draw the waveforms for the Qa, Qb, Qc
signals.
7.5 Given a 100-MHz clock signal, derive a circuit using D FF to generate 50-MHz and
25-MHz clock signals. Draw a timing diagram for all three clock signals, assuming
reasonable delays.
7.6 An SR FF is a FF that has set and reset input like a gated SR latch. Show how an SR
FF can be constructed using a D FF and other logic gates.
7.13 A universal shift register can shift in both the left-to-right and the right-to-left
directions, and it has a parallel-load capability. Draw a circuit for such a shift register.
7.20 Construct a NOR-gate circuit, similar to the one in Figure 7.11a, which implements
a negative-edge-triggered D FF.
Figure P7.1. Timing diagram for problem 7.1.
D
Clock
D Q
Q
D Q
Q
D Q
Q
D
Clock Q
a
Q
b
Q
c
Q
c
Q
b
Q
a
(a) Circuit
Clk
Figure 7.12. Comparison of level-sensitive and edge-triggered D storage elements.
