EE 231 Fall 2007
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Homework #3 Due October 3, 2007
5.1 Determine the decimal values of the following unsigned numbers:
(a) (0111011110)2
(b) (1011100111)2
(c) (3751)8
(d) (A25F)16
(e) (F0F0)16
5.3 Determine the decimal values of the following 2’s complement numbers:
(a) 0111011110
(b) 1011100111
(c) 1111111110
5.5 Perform the following operations involving eight-bit 2’s complement numbers and
indicate whether arithmetic overflow occurs. Check your answers by converting to
decimal sign-and-magnitude representation.
00110110 01110101 11011111
+01000101 +11011110 +10111000
------------ ------------ -----------
00110110 01110101 11011111
- 00101011 -11010110 -11101100
------------ ------------ -----------
5.7 Show that the circuit in Fig. 5.5 implements the full-adder specified in Fig. 5.4a.
5.10 In section 5.5.4 we stated that a carry-out signal, ck, from bit position k-1 of an adder
circuit can be generated as ck=xk yk sk, where xk and yk are inputs and sk is the sum
bit. Verify the correctness of this statement.
5.14 In Fig. 5.18 we presented the structure of a hierarchical carry-lookahead adder.
Show the complete circuit for a four-bit version of this adder, built using 2 two-bit
blocks.
