Dharmsinh Desai University, Nadiad
Faculty Of Technology
B.Tech. Semester III [EC/IC]
Subject: (IC 302)Digital Electronics
Second Sessional ExaminationSyllabus
Textbook Article No. Topics
T1 3.10 Implementation Details for SPLDs, CPLDs
and FPGAs
T1 2.1,2.2 Variables and Functions,
Inversion
T1
2.3,2.4,2.5 Truth Tables, Logic Gates and Networks,
Boolean Algebra
T1 2.6 Canonical and standards
forms
T1
2.6,2.7 Synthesis using AND, OR ,and NOT gates,
NAND and NOR logic Networks
T1
4.1,4.2 Karnaugh Map, Strategy for
Minimization (Up to 4 variables
minimization)
T1
4.3,4.4 Minimization of POS forms and don’t care
conditions
T1 7.8.1 Shift Registers
T1 7.8.2 Parallel Access Shift Registers
T1 8.1.1, 8.1.2 State Diagram, State Table
T1 8.1.3 State Assignment Table
T1 8.1.4 Choice of flip flops, Derivation of state
equations, Circuit Design
T1 8.1.5 Summary, Analysis
T1 8.5 Mealy Machine, Moore machine
T1 8.5 Comparison of Mealy, Moore
Textbook:
T1: Fundamentals of Digital Logic with Verilog Design by Stephen Brown &
Zovonco Vranesic
T2: Digital Logic Computer Design by M. Morris Mano
