Cache Memory Performance-Advance Computer Architecture-Lecture Slides, Slides of Advanced Computer Architecture

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Today’s Topics

Recap: Caching and Locality

Cache Performance Metrics

Cache Designs

Addressing Techniques

Summary

Recap: Memory Hierarchy Principles

High speed storage at the

cheapest cost per byte

Different types of memory

modules are organize in hierarchy,

based on the:

Concept of Caching Principle of Locality

Recap: Principle of Locality

principle of locality

To obtain data or instructions of a

program, the processor access a

relatively small portion of the address

space at any instant of time

Recap: Types of Locality

There are two different types of locality

Temporal locality

Spatial locality

Recap: Working of Memory Hierarchy .. Cont’d

• NOT ONLY do we move the item

that has just been accessed

closer to the processor, but we

ALSO move the data items that

are adjacent to it

Recap: Cache Devices

Cache device is a small SRAM which is made directly accessible to the processor

Cache sits between normal main memory and CPU as data and instruction caches and may be located on CPU chip or as a module

Data transfer between cache - CPU, and cache- Main memory is performed by the cache controller

Cache and main memory is organized in equal sized blocks

Recap: Cache operation

CPU requests contents of main memory location

Controller checks cache blocks for this data

If present, i.e., HIT, it gets data or instruction from cache - fast

If not present, i.e., MISS, it reads required block from main memory to cache, then deliver from cache to CPU

Cache Memory Performance

Miss rate, Miss Penalty, and Average access time are the major trade-off of Cache Memory performance

Miss Rate: is the fraction of memory accesses that are not found in the level-k memory or say the cache number of misses Miss Rate = total memory accesses As, Hit rate is defined as the fraction of memory access that are found in the level-k memory or say the cache, therefore Miss Rate = 1 – Hit Rate

Cache Memory Performance

The performance of a CPU is the product of clock cycle time and sum of CPU clock cycles and memory stall cycles

CPU Execution Time = (CPU Clock Cycles + Memory Stall Cycles) x clock cycle time Where,

memory stall cycles=

= Number of Misses x Miss Penalty

= IC x (Misses / Instructions)x Miss Penalty

= IC x [(Memory Access / Instructions)] x Miss Rate x Miss Penalty

Memory Stall Cycles … cont’d

• Number of cycles for memory read and for memory write may be different,
• Miss penalty for read may be different from the write
• Memory Stall Clock Cycles = Memory read stall cycles + Memory Write stall cycles -