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EECS 141: Fall 2001
Midterm 1
Professor B. Nikolic
For all problems, you can assume the following transistor parameters (unless otherwise mentioned):
NMOS:
Vtn = 0.4, K'n = 115 uA/V^2 , Vdsat = 0.6V, lambda = 0, gamma = 0.4V0.5, 2phif = -0.6V
PMOS:
V (^) tp = -0.4, K'p = -30 uA/V^2 , Vdsat = -1V, lambda = 0, gamma = -0.4V0.5, 2phif = 0.6V
PROBLEM 1. MOS transistor as a switch
Find the final value of the voltage Vo. Assume Vtn = |Vtp|=0.5V. Assume that the
capacitor is initially discarged, and ignore subthreshold conduction and body effect.
PROBLEM 2. Equivalent RC models
In class we modeled the inverter delay by finding its equivalent resistance and capacitance. You are asked to find the equivalent resistance and input capacitiance of a capacitively loaded symmetrically sized inverter.
a) Draw a schematic of how you would measure the equivalent resistance and briefly explain how would you do this.
b) Draw a schematic of how you would measure the equivalent input capacitance of this inverter. Explain the measurement procedure.
c) Does the input capacitance of this inverter depend on its loading? Explain your answer.
d) Does the input capacitance of this inverter depend on the type of transistion (H-L or L-H transition)? If the answer is yes, which one is larger? Explain your answer.
PROBLEM 3. Gate Delays
Consider a three-transistor circuit as shown in the figure below. Vdd = 2.5V and input signal switches between 0 and Vdd with
PROBLEM 4. Wire Modeling
Consider an isolated 2mm long and 1um wide M1 wire over a silicon substrate driven by an inverter with zero output resistance and capacitance.
a) If the wire width is doubled, the delay of this wire will be (circle one):
More than 2x shorter / Exactly 2x shorter / Shorter, but less than 2x / Unchanged / Less than doubled / Exactly doubled / More than doubled
Explanation:
b) If the wire width is halved, the delay of this wire will be (circle one):
More than 2x shorter / Exactly 2x shorter / Shorter, but less than 2x / Unchanged / Less than doubled / Exactly doubled / More than doubled
Explanation:
c) If the wire thickness is doubled, the delay of this wire will be (circle one):
More than 2x shorter / Exactly 2x shorter / Shorter, but less than 2x / Unchanged / Less than doubled / Exactly doubled / More than doubled
Explanation:
d) If the oxide thickness (between the wire and the substrate) is doubled, the wire delay will be (circle one):
More than 2x shorter / Exactly 2x shorter / Shorter, but less than 2x / Unchanged / Less than doubled / Exactly doubled / More than doubled
Explanation:
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