input output in computer arc and org, Slides of Computer Architecture and Organization

The means of exchanging data between the external environment and the computer through input/output (I/O) modules. It explains the three categories of external devices, the International Reference Alphabet (IRA), and the different I/O techniques and commands. It also covers the design issues in implementing interrupt I/O and the characteristics of I/O channels. useful for students studying computer architecture and operating systems.

Typology: Slides

2021/2022

Available from 08/16/2022

SamenKhan
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Input/Output

Overview

I/O Module

Figure 7.1 Generic Model of an I/O Module

Links to

peripheral

devices

Control Lines

Data Lines

Address Lines

System

Bus

Two major functions:

  • Interface to CPU and

Memory

  • Interface to one or more

peripherals

External Devices

Provide a means of exchanging data

between the external environment

and the computer

◼ Attach to the computer by a link to an

I/O module

◼ The link is used to exchange control,

status, and data between the I/O

module and the external device

Peripheral device

◼ An external device connected to an I/O

module

Three categories:

Human readable

◼ Suitable for communicating with the
computer user
◼ Video display terminals (VDTs),
printers

Machine readable

◼ Suitable for communicating with
equipment
◼ Magnetic disk and tape systems,
sensors and actuators

Communication

◼ Suitable for communicating with
remote devices such as a terminal, a
machine readable device, or another
computer

Keyboard/Monitor

◼ Basic unit of exchange is the character

◼ Associated with each character is a code

◼ Each character in this code is represented by a unique 7-bit binary code

◼ 128 different characters can be represented

◼ Characters are of two types:

Printable

◼ Alphabetic, numeric, and special characters that can be printed on paper or displayed on a screen

Control

◼ Have to do with controlling the printing or displaying of characters

◼ Example is carriage return

◼ Other control characters are concerned with communications procedures

Keyboard (Input)

◼ When the user depresses a key it generates an electronic signal that is interpreted by the transducer in the keyboard and translated into the bit pattern of the corresponding IRA code

◼ This bit pattern is transmitted to the I/O module in the computer

Monitor (Output)

◼ On output, IRA code characters are transmitted to an external device from the I/O module

◼ The transducer interprets the code and sends the required electronic signals to the output device either to display the indicated character or perform the requested control function

International Reference Alphabet

(IRA)

Most common means of

computer/user interaction

User provides input through the

keyboard

The monitor displays data

provided by the computer

Status/Control Registers
Data Registers
Interface to
System Bus

Figure 7.3 Block Diagram of an I/O Module

I/O
Logic
Control
Lines
Address
Lines
Data
Lines
External
Device
Interface
Logic
Data
Status
Control
External
Device
Interface
Logic
Data
Status
Control
Interface to
External Device

I/O Module Decisions

  • I/O module may hide the details of timing, formats, and the

electro-mechanics of an external device so that the processor can

function in terms of simple read and write commands, and

possibly open and close file commands.

I/O channel or I/O processor

  • An I/O module that takes on most of the detailed processing

burden, presenting a high-level interface to the processor

(MainFrames)

I/O controller or Device controller

  • An I/O module that is quite primitive and requires detailed

control (Microcomputers)

Input Output Techniques

No Interrupts Use of Interrupts

I/O-to-memory transfer

through processor

Programmed I/O Interrupt-driven I/O

Direct I/O-to-memory

transfer

Direct memory access (DMA)

Table 7.

I/O Techniques

Figure 7.4 Three Techniques for Input of a Block of Data

Issue Read command to I/O module

Read status of I/O module

Check status

Read word from I/O Module

Write word into memory

Done?

Next instruction (a) Programmed I/O

CPU I/O

CPU memory

I/O CPU

I/O CPU

Error condition

Ready Ready

Yes Yes

No

Not ready

Issue Read command to I/O module

Do something else

Read status Interrupt of I/O module

Check status

Read word from I/O Module

Write word into memory

Done?

Next instruction (b) Interrupt-driven I/O

CPU memory

Do something else

Interrupt

CPU DMA

DMA CPU

I/O CPU

Error condition

No

Issue Read block command to I/O module

Read status of DMA module

Next instruction

(c) Direct memory access

CPU I/O

I/O CPU

I/O Mapping Summary

Memory mapped I/O

◼ Devices and memory share an address space

◼ I/O looks just like memory read/write

◼ No special commands for I/O

◼ Large selection of memory access commands available

Isolated I/O

◼ Separate address spaces

◼ Need I/O or memory select lines

◼ Special commands for I/O

◼ Limited set

Interrupt-Driven I/O

The problem with programmed I/O is that the processor has to wait a long time for the I/O module to be ready for either reception or transmission of data

An alternative is for the processor to issue an I/O command to a module and then go on to do some other useful work

The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor

The processor executes the data transfer and resumes its former processing

Start

N + 1

Y + L

N

Y

Y

T

Return

User's Program

Main Memory

Processor

General Registers

Program Counter

Stack Pointer

N + 1

TM

TM

T

Control Stack

Interrupt Service Routine

User's Program

Interrupt Service Routine

(a) Interrupt occurs after instruction at location N (b) Return from interrupt

Figure 7.7 Changes in Memory and Registers for an Interrupt

Start

N + 1

Y + L

N

Y

T

Return

Main Memory

Processor

General Registers

Program Counter

Stack Pointer

Y + L

TM

TM

T

Control Stack

N + 1

Start

N + 1

Y + L

N

Y

Y

T

Return

User's Program

Main Memory

Processor

General Registers

Program Counter

Stack Pointer

N + 1

TM

TM

T

Control Stack

Interrupt Service Routine

User's Program

Interrupt Service Routine

(a) Interrupt occurs after instruction at location N (b) Return from interrupt

Figure 7.7 Changes in Memory and Registers for an Interrupt

Start

N + 1

Y + L

N

Y

T

Return

Main Memory

Processor

General Registers

Program Counter

Stack Pointer

Y + L

TM

TM

T

Control Stack

N + 1

1

2

3

5