Computer Organisation - Input - Output Organization, Study notes of Computer Architecture and Organization

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Input Output Organization

Peripheral Devices

Input Devices

• Keyboard
• Optical input devices - Card Reader - Paper Tape Reader - Bar code reader - Optical Mark Reader
• Magnetic Input Devices - Magnetic Stripe Reader
• Screen Input Devices - Touch Screen - Light Pen - Mouse
• Analog Input Devices

Output Devices

• TFT, LCD, CRT
• Printer (Impact, Ink Jet,

Laser, Dot Matrix)

• Plotter
• Analog
• Voice

I/O Interface

Processor

Interface

Keyboard

Magnetic

tape

Printer

Interface Interface Interface

Data

Address

Control

Magnetic

disk

I/O bus

I/O Interface

• Resolves the differences between the computer

and peripheral devices

▫ Peripherals - Electromechanical Devices

▫ CPU or Memory - Electronic Device

▫ Data Transfer Rate

 Peripherals - Usually slower

 CPU or Memory - Usually faster than peripherals

 Some kinds of Synchronization mechanism may be needed

▫

Unit of Information

 Peripherals – Byte, Block, …

 CPU or Memory – Word

▫ Data representations may differ

I/O Interface

Commands

▫ Control – Start ,Stop, Activate

▫ Status – to get Current Status

▫ Output Data – Transfer data from Processor

▫ Input Data – Transfer data to processor

I/O and Memory Bus

Physical Organization

▫ Many computers use a common single bus

system

for both memory and I/O interface units



Use one common bus but separate control

lines for

each function



Use one common bus with common control

lines

for both functions

▫

Some computer systems use two separate

buses,

Memory Mapped I/O

A single set of read/write control lines

Memory and I/O addresses share the

common address space

No specific input or output instruction

Considerable flexibility in handling I/O

operations

I/O Unit

CS RS1 RS0 Register selected

0 x x None - data bus in high-impeden

1 0 0 Port A register

1 0 1 Port B register

1 1 0 Control register

1 1 1 Status register

Chip select

Register select

Register select

I/O read

I/O write

CS

RS

RS

RD

WR

Timing

and

Control

Bus

buffers

Bidirectional

data bus

Port A

register

Port B

register

Control

register

Status

register

I/O data

Control

Status

Internal

bus

CPU

I/O

Device

I/O data

Programmed I/O

Program-Controlled I/O(Input Dev to CPU)

CPU

Data bus

Address bus

I/O read

I/O write

Interface

Data register

Status

register F

I/O bus

Data valid

Data accepted

I/O

device

Programmed I/O

Polling or Status Checking

• Continuous CPU involvement
• CPU slowed down to I/O speed
• Simple
• Least hardware

Read status register

Check flag bit

flag

Read data register

Transfer data to memory

Operation

complete?

Continue with

program

= 0

= 1

yes

no

Priority Interrupt

What to do when multiple I/O device

interrupt?

▫ Assign Priority to various I/O devices

▫ A higher priority device request is serviced

first

▫ Also determine which devices are

permitted to interrupt the system while

another is being serviced

▫ Higher priority interrupts can make

requests while servicing a lower priority

interrupt

Priority interrupt by software polling

Priority is established by the order of

polling the devices(interrupt sources)

Flexible since it is established by software

Low cost since it needs a very little

hardware

Very slow

Daisy chain

Serially connect all devices

▫ The device with highest priority is placed in

the first position

▫ Interrupt Request from any device(>=1)

-> CPU responds by INTACK <- 1

-> Any device receives signal(INTACK) 1 at PI puts the VAD

on the bus

Device 1

PI PO

Device 2

PI PO

Device 3

PI PO

INT

INTACK

Interrupt request

Interrupt acknowledge

To next

device

CPU

VAD 1 VAD 2 VAD 3

Processor data bus

Parallel Priority Interrupt

• Interrupt Register

▫ Each bit is associated with an Interrupt Request from

different Interrupt Source - different priority level

▫ Each bit can be cleared by a program instruction

• Mask Register

▫ Mask Register is associated with Interrupt Register

▫ Each bit can be set or cleared by an Instruction

• IEN: Set or Clear by instructions ION or IOF
• IST: Represents an unmasked interrupt has

occurred. INTACK enables tristate Bus Buffer to

load VAD generated by the Priority Logic