CS231: Computer Architecture I - Instruction Encoding and Control Units, Study notes of Computer Architecture and Organization

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CS231: Computer Architecture I

Friday, April 27, 2007

-Instruction Encoding-

- Control Unit-

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Instruction encoding

• We’ve already seen some important aspects of processor design.
  • A datapath contains an ALU, registers and memory.
  • Programmers and compilers use instruction sets to issue commands.
• Now let’s complete our processor with a control unit that converts

assembly language instructions into datapath signals.

• Today we’ll see how control units fit into the big picture, and how

assembly instructions can be represented in a binary format.

• On Wednesday we’ll show all of the implementation details for our

sample datapath and assembly language.

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Block diagram of a processor

• The control unit connects programs with the datapath.
  • It converts program instructions into control words for the

datapath, including signals WR, DA, AA, BA, MB, FS, MW, MD.

• It executes program instructions in the correct sequence.
• It generates the “constant” input for the datapath.
• The datapath also sends information back to the control unit. For

instance, the ALU status bits V, C, N, Z can be inspected by branch

instructions to alter a program’s control flow.

Control

Unit

Datapath

Control signals Status signals

Program

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A specific instruction set

• The first thing we must do is agree upon an instruction set.
• For our example CPU let’s stick with the three-address, register-to-

register instruction set architecture introduced in the last lecture.

• Data manipulation instructions have one destination and up to two

sources, which must be either registers or constants.

• We include dedicated load and store instructions to transfer data

to and from memory.

• Next week, we’ll learn about different kinds of instruction sets.

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Register format

• An example register-format instruction:

ADD R1, R2, R

• Our binary representation for these instructions will include:
  • A 7-bit opcode field, specifying the operation (e.g., ADD).
  • A 3-bit destination register, DR.
  • Two 3-bit source registers, SA and SB. Opcode Destination Register (DR) Source Register A (SA) Source Register B (SB)

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Immediate format

• An example immediate-format instruction:

ADD R1, R2,

• Immediate-format instructions will consist of:
  • A 7-bit instruction opcode.
  • A 3-bit destination register, DR.
  • A 3-bit source register, SA.
  • A 3-bit constant operand, OP. Opcode Destination Register (DR) Source Register A (SA) Operand (OP)

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Organizing our instructions

• How can we select binary opcodes for each possible operation?
  • In general, “similar” instructions should have similar opcodes. Again,

this will lead to simpler control unit hardware.

• We can divide our instructions into eight different categories, each

of which require similar datapath control signals.

• To show the similarities within categories, we’ll look at register-based

ALU operations and memory write operations in detail.

Instruction type Register-format ALU operation Register-format shift operation Memory write (from registers) Memory read (to registers) Immediate ALU operation Immediate shift operation Conditional branch Jump

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Register format ALU operations

ADD R1, R2, R

• All register format ALU

operations need the same

values for the following

control signals:

• MB = 0, because all operands

come from the register file.

• MD = 0 and WR = 1, to save

the ALU result back into a

register.

• MW = 0 since RAM is not

modified.

D Register file A B DA AA BA A B ALU G FS V C N Z 1 0 Mux B MB 0 0 1 Mux D MD 0 ADRS DATA Data RAM OUT MW 0 constant WR 1

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Selecting opcodes

• Instructions in each of these categories are similar, so it would be

convenient if those instructions had similar opcodes.

• We’ll assign opcodes so that all instructions in the same category will

have the same first three opcode bits (bits 15-13 of the instruction).

• Next time we’ll talk about the other instruction categories shown here. Opcode bits Instruction type 15 14 13 Register-format ALU operation 0 0 0 Register-format shift operation 0 0 1 Memory write (from registers) 0 1 0 Memory read (to registers) 0 1 1 Immediate ALU operation 1 0 0 Immediate shift operation 1 0 1 Conditional branch 1 1 0 Jump 1 1 1

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ALU and shift instructions

• What about the rest of the opcode bits?
• For ALU and shift operations, let’s fill in

bits 12-9 of the opcode with FS3-FS0 of

the five-bit ALU function select code.

• For example, a register-based XOR

instruction would have the opcode

• The first three bits 000 indicate a

register-based ALU instruction.

• 1100 denotes the ALU XOR function.
• An immediate shift left instruction would

have the opcode 1011000.

• 101 indicates an immediate shift.
• 1000 denotes a shift left. FS Operation 00000 F = A 00001 F = A + 1 00010 F = A + B 00011 F = A + B + 1 00100 F = A + B’ 00101 F = A + B’ + 1 00110 F = A – 1 00111 F = A (^01000) F = A!^ B (AND) (^01010) F = A "^ B (OR) 01100 F = A #^ B 01110 F = A’ 10000 F = B 10100 F = sr B (shift right) 11000 F = sl B (shift left)

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Sample opcodes

• Here are some more examples of instructions and their corresponding

opcodes in our instruction set.

• Several opcodes have unused bits.
  • We only need three bits to distinguish eight types of branches.
  • There is only one kind of jump and one kind of load instruction.
• These unused opcodes allow for future expansion of the instruction set.

For instance, we might add new instructions or new addressing modes.

Instruction Opcode bits ( 15 - 13 ) Opcode bits ( 12 - 9 ) LD R 1 , (R 0 ) 011 (load) xxxx (unused) BZ R 1 , + 4 110 (branch) x 011 (branch on zero) SUB R 5 , R 5 , # 1 100 (immediate arithmetic) 0100 (subtract) ADD R 1 , R 0 , R 5 000 (register arithmetic) 0010 (add) JMP – 3 111 (jum p) xxxx (unused)

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Summary

• Today we defined a binary machine language for the instruction set

from last week.

• Different instructions have different operands and formats, but

keeping the formats uniform will help simplify our hardware.

• We also try to assign similar opcodes to “similar” instructions.
• The instruction encodings and datapath are closely related. For

example, our opcodes include ALU selection codes, and the number

of available registers is limited by the size of each instruction.

• This is just one example of how to define a machine language.
• On Wednesday we’ll show how to build a control unit corresponding to

our datapath and instruction set. This will complete our processor!

Control Unit 1919

Where does the program go?

• We’ll use a Harvard architecture, which includes two memory units.

– An instruction memory holds the program.

– A separate data memory is used for computations.

– The advantage is that we can read an instruction and load or

store data in the same clock cycle.

• For simplicity, our diagrams do not show any WR or DATA inputs to the

instruction memory.

• Caches in modern CPUs often feature a Harvard architecture like this.

• However, there is usually a single main memory that holds both program

instructions and data, in a Von Neumann architecture.

ADRS Instruction RAM OUT ADRS DATA Data RAM OUT MW

Control Unit 2020

Program counter

• A program counter or PC addresses the instruction memory, to keep track of the instruction currently being executed.
• On each clock cycle, the counter does one of two things.
  • If Load = 0, the PC increments, so the next instruction in memory

will be executed.

• If Load = 1, the PC is updated with Data, which represents some

address specified in a jump or branch instruction.

ADRS Instruction RAM OUT Load PC Data