Instructions types in computer architecture, Lecture notes of Computer Architecture and Organization

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Cosc 3P

Week 4 Lecture slides

It is the mark of an educated mind to be able to entertain

a thought without accepting it.

Aristotle

Computer Instruction Set

• An instruction has two components:

• (^) e.g

• The operand field may have the following

formats:

1. zero-address
2. one-address
3. two-address
4. three-address

• The total number of instructions and the types

and formats of the operands determine the

length of an instruction.

. Op-code Operand(s) ADD R0^100

Bits/cell (word)

Instruction sets

• Byte ordering

• (^) Big-endian: bytes in word ordered from left-to-right eg. Motorola
• (^) Little-endian: bytes in word ordered right-to-left eg. Intel

• Creates havoc when transferring data; need to

swap byte order in transferred words.

Op-code Encoding

• 1. Block-code technique

• (^) To each of the 2K^ instructions a unique binary bit pattern of length K is assigned.
• (^) An K-to-2K^ decoder can then be used to decode all the instructions. For example, 3-to- 3-bit Op-code decoder instruction 0 instruction 1 instruction 2 instruction 3 instruction 4 instruction 5 instruction 6 instruction 7

Op-code Encoding

• 2. Expanding op-code technique

• (^) Consider an 4+12 bit instruction with a 4-bit op-code and three 4-bit addresses.
• (^) It can at most encode 16 three-address instructions.
• (^) If there are only 15 such three-address instructions, then one of the unused op-code can be used to expand to two-address, one-address or zero address instructions
• (^) Again, this expanded op-code can encode at most 16 two-address instructions. And if there are less than 16 such instructions, we can expand the op-code further. Op-code Address 1 Address 2 Address 3 1 1 1 1 Op-code Address 1 Address 2 1 1 1 1 1 1 1 1 Op-code Address 1 1 1 1 1 1 1 1 1 1 1 1 1^ Op-code

Op-code Encoding

• Huffman encoding

• (^) Given the probability of occurrences of each instruction, it is possible to encode all the instructions with minimal number of bits, and with the following property: Fewer bits are used for most frequently used instructions and more for the least frequently used ones. 1 1/ 1/ 1/8 1/8^ 1/4^ 1/ 1/16 1/16 1/16 1/16 1/8 1/8 1/4 1/ HALT JUMP SHIFT NOT AND ADD STO LOAD 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0000 0001 0010 0011 010 011 10 11

Opcode encoding,

Huffman codes

• Huffman encoding algorithm:

• (^) 1. Initialize the leaf nodes each with a probability of an instruction. All nodes are unmarked.
• (^) 2. Find the two unmarked nodes with the smallest values and mark them. Add a new unmarked node with a value equal to the sum of the chosen two.
• (^) 3. Repeat step (2) until all nodes have been marked except the last one, which has a value of 1.
• (^) 4. The encoding for each instruction is found by tracing the path from the unmarked node (the root) to that instruction.

• may mark branches arbitrarily with 0, 1

Addressing modes

• inherent

• (^) an op-code indicates the address of its operand CLI ; clear the interrupt flag

• immediate

• (^) an instruction contains or immediately precedes its operand value ADD #250, R1 % R1 := R1 + 250;

• Absolute/Direct

• (^) an instruction contains the memory address of its operand ADD 250, R1 % R1 := R1 + *(250);

• register

• (^) an instruction contains the register address of its operand ADD R2, R1 % R1 := R1 + R2;

Addressing Modes

• register indirect

• (^) the register address in an instruction specifies the address of its operand ADD @R2, @R1 % *R1 := *R1 + *R2;

• auto-decrement or auto-increment

• (^) The contents of the register is automatically decremented or incremented before or after the execution of the instruction MOV (R2)+, R1 % R1 := *(R2); R2 := R2 + k; MOV -(R2), R1 % R2 := R2 - k; R1 := *(R2);

Addressing modes

• Indirect addressing mode in general also applies

to absolute addresses, not just register

addresses; the absolute address is a pointer to

the operand.

• The offset added to an index register may be as

large as the entire address space. On the other

hand, the displacement added to a base register

is generally much smaller than the entire address

space.

• The automatic modification (i.e., auto-increment

or auto-decrement) to an index register is called

autoindexing.

• Relative addresses have the advantage that the

code is position-independent.

Instruction Types

• Instructions, of most modern computers, may be

classified into the following six groups:

• (^) Data transfer (40% of user program instructions) MOV, LOAD
• (^) Arithmetic ADD, SUB, DIV, MUL
• (^) Logical AND, OR, NOT, SHIFT, ROTATE
• (^) System-control Test-And-Set
• (^) I/O Separate I/O space input/output

Instruction types

• (^) Typical branch instructions
  • (^) test the value of some flags called conditions.
  • (^) Certain instructions cause these flags to be set automatically.
• (^) linkage registers
  • (^) Used in implementing a subroutine.
  • (^) Typically include the instruction pointer and stack pointer..
• (^) The parameters passed between the caller and the called

subroutine are to be established by programming conventions.

• (^) Very few computers support parameter-passing mechanisms in the hardware.
• (^) An external interrupt may be regarded as a hardware generated

subroutine call

• (^) Can happen asynchronously.
• (^) When it occurs, the current state of the computation must be saved either by » (^) the hardware automatically » (^) or by a program (interrupt-service routine) control.

Examples: Intel Pentium

• back-compatible to 8088 (16 bit, 8 bit data bus), X

8086 (16 bit), 80286 (16 bit, larger addr), 80386 (

bit), ...

• Based on IA-32 (instruction archetecture 32bit)

• 3 operating modes:

1. real mode - acts like 8088 (unsafe -- can crash)
2. virtual 8086 - protected
3. protected - acts like Pentium II + 4 privilege levels too (kernel, user, ...)

• little endian words

• registers: [5.3]

• (^) EAX, EBX, ECX, EDX - general purpose, but have special uses (eg. EAX = arithmetic, ...)
• (^) ESI, EDI, EBP, ESP - addr registers