MIPS Computer Architecture: Instructions and Addressing Modes, Slides of Computer Architecture and Organization

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Lecture 04- Decision

Instructions

EE

Computer Architecture

 Instructions, like registers and words of data, are 32 bits long  (^) Arithmetic Instruction Format (R format): add $t0, $s1, $s

Recap: Add Instruction

op rs rt rd shamt funct op 6-bits opcode that specifies the operation rs 5-bits register file address of the first source operand rt 5-bits register file address of the second source operand rd 5-bits register file address of the result’s destination shamt 5-bits shift amount (for shift instructions) funct 6-bits function code augmenting the opcode

Aside: Loading and Storing

Bytes

 MIPS provides special instructions to move bytes lb $t0, 1($s3) #load byte from memory sb $t0, 6($s3) #store byte to memory op rs rt 16 bit offset  (^) What 8 bits get loaded and stored?  (^) load byte places the byte from memory in the rightmost 8 bits of the destination register

• (^) what happens to the other bits in the register?  (^) store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory
• (^) what happens to the other bits in the memory word?

x

Loading, Storing bytes

What do with other 24 bits in the 32 bit register? lb: sign extends to fill upper 24 bits

byte

loaded

…is copied to “sign-extend”

This bit

xxxx xxxx xxxx xxxx xxxx xxxx zzz zzzz

• Normally don’t want to sign extend chars

• (^) MIPS instruction that doesn’t sign extend when

loading bytes:

load byte unsigned: lbu

 MIPS conditional branch instructions: bne $s0, $s1, Lbl#go to Lbl if $s0$s beq $s0, $s1, Lbl#go to Lbl if $s0=$s  (^) Ex: if (i==j) h = i + j; bne $s0, $s1, Lbl add $s3, $s0, $s Lbl1: ...

MIPS Control Flow

Instructions

 (^) Instruction Format (I format): op rs rt 16 bit offset  (^) How is the branch destination address specified?

Specifying Branch Destinations

Use a register (like in lw and sw) added to the 16-bit offset which register? Instruction Address Register (the PC) its use is automatically implied by instruction PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction limits the branch distance to -2^15 to +2^15 -1 instructions from the (instruction after the) branch instruction, but most branches are local anyway PC Add 32 32 32 32 32 offset 16 32 00 sign-extend from the low order 16 bits of the branch instruction branch dst address ? Add 4 32

More Branch Instructions,

Con’t

Can use slt, beq, bne, and the fixed value of 0 in register $zero to create other conditions less than blt $s1, $s2, Label less than or equal to ble $s1, $s2, Label greater than bgt $s1, $s2, Label great than or equal to bge $s1, $s2, Label slt $at, $s1, $s2 #$at set to 1 if bne $at, $zero, Label # $s1 < $s  (^) Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler  (^) Its why the assembler needs a reserved register ($at)

 MIPS also has an unconditional branch instruction or jump instruction: j label #go to label

Other Control Flow Instructions

 (^) Instruction Format (J Format): op 26-bit address PC 4 32 26 32 00 from the low order 26 bits of the jump instruction

 MIPS procedure call instruction: jal ProcedureAddress#jump and link  (^) Saves PC+4 in register $ra to have a link to the next instruction for the procedure return  (^) Machine format (J format):  (^) Then can do procedure return with a jr $ra #return  Instruction format (R format):

Instructions for Accessing

Pocedures

op 26 bit address 13 op^ rs^ funct

Aside: Spilling Registers

What if the callee needs more registers? What if the procedure is recursive? uses a stack – a last-in-first-out queue – in memory for passing additional values or saving (recursive) return address(es)^ One of the general registers, $sp, is used to address the stack (which “grows” from high address to low address)  (^) add data onto the stack – push $sp = $sp – 4 data on stack at new $sp  (^) remove data from the stack – pop data from stack at $sp $sp = $sp + 4 low addr high addr top of stack $sp

 We'd also like to be able to load a 32 bit constant into a register, for this we must use two instructions  (^) a new "load upper immediate" instruction lui $t0, 1010101010101010  (^) Then must get the lower order bits right, use ori $t0, $t0, 1010101010101010

Aside: How About Larger

Constants?

16 0 8 1010101010101010 1010101010101010 0000000000000000 1010101010101010 0000000000000000 1010101010101010 1010101010101010

MIPS Organization So Far

Processor Memory 32 bits 230 words read/write addr read data write data word address (binary) 0… 0… 0… 0… 1… Register File src1 addr src2 addr dst addr write data 32 bits src data src data 32 registers ($zero - $ra) 32 32 32 32 32 32 5 5 5 PC ALU 32 32 32 32 32 0 1 2 3 4 5 6 7 byte address (big Endian) Fetch PC = PC+ Exec Decode Add 32 32 4 Add 32 32 branch offset

Review of MIPS Operand Addressing Modes Register addressing – operand is in a register Base (displacement) addressing – operand is at the memory location whose address is the sum of a register and a 16-bit constant contained within the instruction Register relative (indirect) with 0($a0) Pseudo-direct with addr($zero) Immediate addressing – operand is a 16-bit constant contained within the instruction op rs rt rd funct (^) Register word operand base register op rs rt offset (^) Memory word or byte operand op rs rt operand 19

Review of MIPS Instruction

Addressing Modes

PC-relative addressing –instruction address is the sum of the PC and a 16-bit constant contained within the instruction Pseudo-direct addressing – instruction address is the 26-bit constant contained within the instruction concatenated with the upper 4 bits of the PC op rs rt offset Program Counter (PC) Memory branch destination instruction op jump address Program Counter (PC) Memory || jump destination instruction