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Material Type: Notes; Class: Computer Architecture; Subject: Computer Science; University: University of Utah; Term: Unknown 1989;
Typology: Study notes
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Topics: topologies, routing, deadlocks, flow control
Final exam reminders:
Plan well โ attempt every question ย 10 questions, 4 of them โnewโ ย 16% on pre-midterm material ย Caches, multiprocs, TM (no interconnection networks) ย 9-10:40am ย Laptops and any class material allowed
Deterministic routing: given the source and destination, there exists a unique route
Adaptive routing: a switch may alter the route in order to deal with unexpected events (faults, congestion) โ more complexity in the router vs. potentially better performance - Example of deterministic routing: dimension order routing: send packet along first dimension until destination co-ord (in that dimension) is reached, then next dimension, etc.
Packets of message 1 Packets of message 2 Packets of message 3 Packets of message 4 4-way switch Output ports Each message is attempting to make a left turn โ it must acquire an output port, while still holding on to a series of input and output ports Input ports
Number edges and show that all routes will traverse edges in increasing (or^ decreasing) order โ therefore, it will be impossible to have cyclic dependencies - Example: k-ary 2-d array with dimension routing: first route along x-dimension,^ then along y 1 2 3 2 1 0 1 2 3 2 1 0 1 2 3 2 1 0 1 2 3 2 1 0 17 18 19 18 17 16
Consider the eight possible turns in a 2-d array (note that^ turns lead to cycles)
By preventing just two turns, cycles can be eliminated - Dimension-order routing disallows four turns - Helps avoid deadlock even in adaptive routing West-First North-Last Negative-First Can allow deadlocks
A message is broken into multiple packets (each packet has header information that allows the receiver to re-construct the original message)
A packet may itself be broken into flits โ flits do not contain additional headers - Two packets can follow different paths to the destination Flits are always ordered and follow the same path - Such an architecture allows the use of a large packet size (low header overhead) and yet allows fine-grained resource allocation on a per-flit basis
A buffer between two channels decouples the resource allocation for each channel โ buffer storage is not as precious a resource as the channel (perhaps, not so true for on-chip networks)
Packet-buffer flow control: channels and buffers are allocated per packet
Store-and-forward ย Cut-through Time-Space diagrams H B B B T H B B B T H B B B T 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Cycle Channel 0 1 2 3 Channel H B B B T H B B B T H B B B T 0 1 2 3
Wormhole Flow Control: just like cut-through, but with buffers allocated per flit (not channel)
A head flit must acquire three resources at the next^ switch before being forwarded:
channel control state (virtual channel, one per input port) ย one flit buffer ย one flit of channel bandwidth The other flits adopt the same virtual channel as the head and only compete for the buffer and physical channel ย Consumes much less buffer space than cut-through^ routing โ does not improve channel utilization as another^ packet cannot cut in (only one VC per input port)
Wormhole: - Virtual channel: A B B A is going from Node-1 to Node-4; B is going from Node-0 to Node- Node- Node- Node- (blocked, no free VCs/buffers) Node- Node- Node- idle idle A B A Node- Node- Node- (blocked, no free VCs/buffers) Node- Node- Node- B A Traffic Analogy:^ B is trying to make^ a left turn; A is trying^ to go straight; there^ is no left-only lane^ with wormhole, but^ there is one with VC
Credit-based: keep track of the number of free buffers in^ the downstream node; the downstream node sends back^ signals to increment the count when a buffer is freed;^ need enough buffers to hide the round-trip latency
On/Off: the upstream node sends back a signal when its^ buffers are close to being full โ reduces upstream^ signaling and counters, but can waste buffer space
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