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EEE 531: Semiconductor Device Theory I
EEE 531: Semiconductor Device Theory I
Instructor: Dragica Vasileska
Department of Electrical Engineering
Arizona State University
Topics covered:
1. Introduction **(band diagrams, fields and dielectrics)
- MOS Capacitor Electrostatics** (A) Block-charge model (B) Exact analytical model (C) Self-consistent solutions (SCHRED)
EEE 531: Semiconductor Device Theory I
1. Introduction
- The Si MOSFET is the most important solid-state device
for modern electronics. To understand its operation, we
first need to understand the MOS capacitors:
Semiconductor (p-type or n-type)
V metal
oxide
oxide thickness dox
EEE 531: Semiconductor Device Theory I
- Energy-band diagram of ideal MOS capacitor , for which:
M sc
E (^) FM EFS
Φ (^) M Φsc (^) sc χ
Vacuum level
F
g M sc q
E
Φ =χ + − ϕ 2
qϕ F
E C
E V
n-type semiconductor
F
g M sc q
E
Φ =χ + + ϕ 2
p-type semiconductor
E i
E FM (^) EFS
Φ M
Φ (^) sc sc χ
qϕ F
E C
E V
E i
EEE 531: Semiconductor Device Theory I
- Ideal MOS capacitor under accumulation bias conditions:
p-type SC
G
−V
holes
d ox
−Q G
S
Q
FM
E
E FS
E C
E V
E i
Accumulation of majority holes
G qV ρ(x )
x
x-axis
Energy
EEE 531: Semiconductor Device Theory I
(a) Bulk potential:
p-type SC:
n-type SC:
(b) Potential:
(c) Surface potential:
Wf
FS
E
C
E
E V
i
E
q ϕ F
q ϕ s
q ϕ ( x ) q^ ϕ^ F =Ei(bulk)−EFS
ln > 0
ϕ = i
B A F n
N
q
kT
ln (^) < 0
ϕ =− i
B D F n
N
q
kT
q ( x) E(bulk) E(x ) i i ϕ = −
q ϕs =Ei( bulk)−Ei( 0 )
ϕ s
ϕ( x )
x
EEE 531: Semiconductor Device Theory I
- Regions of operation for MOS capacitor with p-type SC:
(a) accumulation:
(b) depletion:
(c) inversion:
- The condition ϕs=2 ϕF is called onset of inversion :
ϕ < 0 s
s F 0 < ϕ < 2 ϕ
s F ϕ ≥ 2 ϕ
(^) ϕ = −
ϕ =
2
exp
exp
exp
exp
s s i
s
B
F i B
i FS s i
B
F i B
FS i s i
np n
n pbulk
k T
q n k T
E E
p n
k T
q n k T
E E
n n
EEE 531: Semiconductor Device Theory I
- Fields and dielectrics:
- Electric field profile for a
MOS capacitor with p-
type SC under depletion
condition:
10 kε
2 0 k ε
t 1
F
Ft 2
t 1 t 2
F =F
Tangential components
k 1 ε 0
20 k ε
n 1
F
n 2
F
10 1 20 2
1 2
n n
n n k F k F
D D
ε = ε
Normal components
d o x
F(x )
x do x +W f
F o x
F sc
Fox ≈ 3 F sc
EEE 531: Semiconductor Device Theory I
EEE 531: Semiconductor Device Theory I
Instructor: Dragica Vasileska
(Notes provided by: Prof. Dieter Schroder)
Department of Electrical Engineering
Arizona State University
Topics covered:
2. MOS Capacitor Electrostatics (A) Block-charge model (B) Exact analytical model (C) Self-consistent solutions (SCHRED)
EEE 531: Semiconductor Device Theory I
Depletion:
−d o x
Q G
ρ( x )
x
W
Q (^) s =−qNA W
ϕs
x
ϕ( x )
0
- The charge density is given by:
- The boundary conditions for the 1D Poisson equation are:
- Final expressions for the electric field, electrostatic potential and the width of the depletion region:
A ρ (x )=−qN
ϕ (W )=F(W)= 0 ,ϕ( 0 )=ϕ s
A
s s
s
A
s
A
qN
k W
W x k
qN x
W x k
qN F x
ε ϕ
ε
ϕ =
ε
0
2
0
0
G s ox
VG V =ϕ +V
EEE 531: Semiconductor Device Theory I
- The surface potential is an internal parameter. We therefore
need to relate ϕs to the gate voltage VG using:
where:
- Final expression for the VG-ϕs relationship:
- Threshold voltage definition:
VG =Vox+ϕs=Foxdox+ϕ s
0 0 ε
ε
ox
A
s
A
ox
s s ox
s ox k
qN W
k
qN W
k
k F k
k F
ox
ox A s s ox ox
G s d
k qN k C C
V
0 2 0 , where
1 ε =ϕ + εϕ =
Vth = VG for which ϕs= 2 ϕ F
EEE 531: Semiconductor Device Theory I
- Graphical representation of the VG-ϕs relationship:
ϕs ϕ (^) s = 2 ϕ F
G
V
V th
Exact solution
Delta-depletion approximation
- Surface potential varies rapidly with VG when the device is depletion biased. Gate voltage is divided proportionally between the semiconductor and the oxide.
- When the semiconductor is accumulated or inverted , it takes large VG to produce small change in ϕs. Changes in the applied bias are almost all dropped across the oxide.
EEE 531: Semiconductor Device Theory I
(B) Exact Analytical Model
- To solve for the electrostatic potential and the electric field
profile under arbitrary bias conditions, one needs to go
beyond the delta-depletion approximation and use the exact
expression for the charge density ρ(x) in the 1D Poisson
equation:
- Analytical tricks that we need to use to get to the answer:
(2) in the semiconductor bulk, where ϕ=0.
( )
( (^) D A)
V po
V po
D A
qp e n e N N
x q p n N N
= T^ −^ T+ −
ρ = − + −
− ϕ/ ϕ/
2
2
F x dx
d u d
udu
dx
d
dx
d
d
d
dx
d
dx
d
dx
d =−
ϕ
ϕ
ϕ
ϕ
ϕ
ϕ
ϕ
ρ( x)= 0
EEE 531: Semiconductor Device Theory I
- The corresponding gate voltage equals to:
- Simulation results for NA= 16
cm
and dox=4 nm:
s ox ox
s G s ox s Fd k
k V =ϕ +V =ϕ +
-1.
-0.
0
1
2
-0.4 -0.2 0 0.2 0.4 0.6 0.8 1
V G^
[V]
ϕs [V]
2 ϕ F
VG = VTH≈ 0. 7 V
Delta approximation
ϕF= 0. 35 V
Surface potential
-2 10^12
-1.5 10^12
-1 10^12
-5 10^11
0
5 10^11
1 10^12
1.5 10^12
2 10^12
-0.4 -0.2 0 0.2 0.4 0.6 0.8 1
|Q
/q| [cms
-2]
Surface potential ϕs [V]
accumulation
depletion inversion
Sheet-charge density
EEE 531: Semiconductor Device Theory I
(C) SCHRED: Self-Consistent Schrödinger-Poisson Solver
http://www.ecn.purdue.edu/labs/punch/
- Existing SCHRED Features:
Ë Classical and quantum-mechanical charge description
Fermi-Dirac and Maxwell-Boltzmann Statistics (for classical) Fermi-Dirac for quantum-mechanical calculation
Ë Single-valley and multiple-valley conduction bands
Ë Metal and poly-silicon gates
Ë Partial ionization of the impurity atoms
Ë Exchange and correlation corrections to the ground
state energy of the system
EEE 531: Semiconductor Device Theory I
Read data from input file
Solve Poisson’s equation
Update ρ(x)
no
Solve 1D Poisson’s equation
Update ρ(x)
no
Solve 1D Schrödinger equation
classical quantum
Converged?
Write data in files
Converged?
yes
yes
EEE 531: Semiconductor Device Theory I
0
1
2
3
4
0 10 20 30 40 50 60 70 80
E
c^
[eV]
depth [nm]
Classical charge distribution: NA=10^18 cm-3, dox=4 nm VG=1 V
Referent level is the Fermi level (EF=0)
Conduction band edge:
0
1 10^19
2 10^19
3 10^19
4 10^19
5 10^19
10 15 20 25 30
n [cm
]
depth [nm]
Classical charge distribution NA=10^18 cm-
Electron density:
-1 10^19
-8 10^18
-6 10^18
-4 10^18
-2 10^18
0
0 1 0 20 3 0 40 5 0 60 7 0 80
ρ
(x)/q [cm
]
Depth [nm]
semiconductor charge
Charge density:
EEE 531: Semiconductor Device Theory I
- In general, the charge in the semiconductor is represented
as a sum of the inversion layer charge density QN, depletion
layer charge density QB and the accumulation layer charge
density QP, which gives:
- The total gate capacitance is, thus, given by:
inv depl acc s
P
s
B
s
N
s
s s C C C d
dQ
d
dQ
d
dQ
d
dQ C = + + ϕ
− ϕ
− ϕ
=− ϕ
=−
ox
ox ox
inv depl acc
ox
ox
ox s
ox tot
d
k C
C C C
C
C
C C
C
C
0
ε
Cox
Semiconductor Cinv Cdepl C^ acc capacitance Cs
EEE 531: Semiconductor Device Theory I
- Using the analytical model expression for the semiconduc-
tor charge per unit area Qs, we get:
(A) Accumulation regime:
( )
1 / 2 / /
/ /
( ) 1 1
2 ( )
1 1
−
ϕ − + −
ϕ ϕ = +
ϕ
− + −
= ϕ
=−
−ϕ ϕ
−ϕ ϕ
T
V s
po
po
T
V s s
s
V
po
V po
s
s s
V
e p
n
V
f e
f
e p
n e
Cso d
dQ C
s T s T
s T s T
→
ε
D
s so L
k C 0
Flat-band capacitance
( ) tot ox N B
s s s T C C dQ dQ
f V → ≈
= =
ϕ < → ϕ ∝ −ϕ
0 , 0
0 ( ) exp / 2
The total gate capacitance is approximately equal to the
oxide capacitance.
EEE 531: Semiconductor Device Theory I
(B) Depletion regime:
In depletion regime, the inversion charge is negligible when
compared to the depletion charge. Hence:
The total capacitance is, thus, given by:
Important remarks:
Ë If NA increases, then Ctot increases.
Ë If dox increases, Ctot decreases.
s
s A
s T
s N P
s F s s T k qN V
Cso C dQ dQ
f V
ϕ
ε
ϕ
→ =
= =
<ϕ < ϕ → ϕ ∝ ϕ
0 , (^02) / 2
0 2 ( ) / 0
s A
s ox ox
ox
depl
ox
ox
s
ox
ox tot
k qN
d k
k
C
C
C
C
C
C
C
0
0
0
2 1 1 ε
ϕ
ε
EEE 531: Semiconductor Device Theory I
(C) Inversion regime:
- Most of the charge induced at the
SC-oxide interface comes from the electron-hole pair generation (via recombination-generation centers).
- The build-up of minority carriers
proceeds at a rate limited by the process of generation of electron- hole pairs.
- Hence, depending upon the
frequency of the applied signal and the sweep-rate of the gate voltage, one can measure:
- low-frequency (LF) CV -curves
- high-frequency (HF) CV -curves
- deep-depletion (DD) CV -curves
G qV
W
E FS
E C
E V
E i
EEE 531: Semiconductor Device Theory I
High-frequency CV-curve:
- AC-frequency high, which pre-
vents the response of the mino-
rity carriers. The sweep-rate is
low, thus allowing for the gene-
ration of the inversion layer
electrons.
- Depletion layer and total gate capacitance:
F
s A s depl N P
s F s F T k qN C C dQ dQ
f V
ϕ
ε → ≈ ≈
ϕ ≈ ϕ → ϕ = ϕ
0
const
k qN
C
C
C C
C
C
s A
F ox
ox
ox depl
ox tot
ε
ϕ
0
Q G
x
W f
Q s
EEE 531: Semiconductor Device Theory I
Deep-depletion CV-curve:
- AC-frequency high, which pre-
vents the response of the mino-
rity carriers. The sweep-rate is
also high, thus preventing the
generation of the inversion layer
electrons.
- Depletion layer and total gate capacitance:
s
s A s depl N P
s s T k qN C C dQ dQ
f V
ϕ
ε → ≈ ≈
= =
ϕ = ϕ
0 , (^02)
( ) / 0
s A
s ox
ox
depl
ox
ox tot
k qN
C
C
C
C
C
C
0
0
Q G
x
W
Q s
EEE 531: Semiconductor Device Theory I
What is low-frequency?
- The SCR generation current density equals to:
- While JSCR flows in the semiconductor, the current flowing through the
oxide is:
- For the inversion charge to be able to respond, we must have that the
SCR current must be able to supply the required displacement current, i.e.
Example: dox=100 nm, W=1 μm, Cox=3.45× 10 -8^ F/cm^2 :
τg=10 μs, dV/dt ≤ 0.65 V/s, feff=45 Hz (not a severe constraint)
τg=1 ms, dV/dt ≤ 6.5 mV/s, feff=0.4 Hz (severe constraint)
J (^) SCR = qniW/τ g
J (^) D =CoxdV/ dt
ox g
i ox i g C
qnW C dV dt qnW dV dt τ
/ ≤ /τ → / ≤
EEE 531: Semiconductor Device Theory I
(D) SCHRED Capabilities:
- Capable of modeling MOS capacitors with p-type
substrates
- SCHRED is able to calculate separately the inversion
layer capacitance Cinv and the depletion layer capaci-
tance Cdepl
- SCHRED also gives as an output the LF gate capacitance
- With simple post-processing, one can also calculate the
HF gate capacitance, using:
depl
ox
ox
s
ox
ox tot
C
C
C
C
C
C
C
EEE 531: Semiconductor Device Theory I
4. Deviations from the ideal model
There are several factors that lead to deviation of the
measured CV-curves from what the ideal model predictions
are:
- Work-function difference
- Oxide charges (interface-trap, fixed-oxide, oxide-trap
and mobile oxide charges)
- Depletion of the poly-silicon gates
- Quantum-mechanical space-quantization effects
EEE 531: Semiconductor Device Theory I
(A) Work-function difference:
F
g M sc q
E
Φ =χ + + ϕ 2
Ideal MOS capacitor with a p-type semiconductor
E (^) FM EFS
Φ M
Φ SC (^) SC χ
qϕ F
E C
E V
E i
W
E FM (^) EFS
E C
E V
E i
Real MOS capacitor with a p-type semiconductor
−V (^) FB=ΦSC−Φ M
Φ M
Φ SC
EEE 531: Semiconductor Device Theory I
- The flat-band voltage VFB equals the required gate voltage
to achieve flat-band conditions.
- The workfunction difference modifies the relationship
between the surface potential and the applied bias. This
gives rise to threshold voltage shift between the ideal and
real CV-curves:
( ) G G G MS M SC q q
∆V =V −V = Φ = Φ −Φ
'^11
Voltage applied to real
MOS capacitor
Voltage applied to ideal
MOS capacitor
EEE 531: Semiconductor Device Theory I
- Influence on the LF CV-curves:
- Same effect is also observed on the HF and the DD CV-
curves.
0
1
-1.5 - 1 -0.5 0 0.5 1 1.5 2
Ideal MOS capacitor non-ideal MOS capacitor
Capacitance [
μF/cm
2 ]
Gate voltage [V]
N (^) A=10^16 cm- 3 ∆VG C to x = 4 nm FB
