Download Exam Solutions for Computer Engineering (ECE 2030B) - Fall 2003 - Problem 1 to 4 and more Exams Electrical and Electronics Engineering in PDF only on Docsity!
4 problems, 4 pages Exam Two Solutions 22 October 2003
Problem 1 (3 parts, 32 points) Representations and Arithmetic
Part A (15 points) For the 24 bit representations below, determine the most negative value, most positive value, and step size (difference between sequential values). All answers should be expressed in decimal notation. Fractions (e.g., 3/16ths) may be used. All signed representations are two’s complement.
representation most negative value most positive value step size
signed integer (24 bits). (0 bits)
-8M +8M 1
unsigned fixed-point (12 bits). (12 bits)
0 4K 1/4K
unsigned fixed-point (16 bits). (8 bits)
0 64K 1/
signed fixed-point (16 bits). (8 bits)
-32K +32K 1/
Part B (8 points) For each problem below, compute the operations using the rules of arithmetic, and indicate whether an overflow occurs assuming all numbers are expressed using a six bit two’s complement fixed-point representation.
result 001.100 100.000 100.000 111.
signed error?
no no yes no
Part C (9 points) Answer the following questions for the single precision floating point representation discussed in class (1 sign bit, 23 mantissa bits, 8 exponent bits).
range of mantissa values (in decimal): 0 to^1
largest represented value (power of two): 2
approx. number of decimal significant figures: (2 23 = 8,000,000) 7 sigfigs
4 problems, 4 pages Exam Two Solutions 22 October 2003
Problem 2 (3 parts, 21 points) Building Blocks
Part A (8 points) Implement a 2 to 4 decoder using only AND gates. Assume inputs signals IN 0 , IN 1 , and En and their complements are available. Label all inputs and outputs.
En In 0 In 1
Out 3
En In 0 In 1
Out 2
En
Out 1
En In 0 In 1
In 0 Out 0 In 1
Part B (9 points) Complete the truth table below to describe the behavior of the following circuit.
2 to 4
decoder
In 0 In 1 En
Out 0 Out 1 Out 2 Out 3
A
B
C
D
Out
Y
1
Z
D C B A Z Y Out
1 1 1 0 0 0 0 (A)
1 1 0 0 1 0 1 (C)
0 0 1 1 0 1 1 (B)
0 1 0 0 0 1 0 (B)
1 1 0 0 1 0 1 (C)
0 1 0 1 1 1 0 (D)
Part C (4 points) Name the building block implemented in part B.
It’s a 4 to 1 multiplexer
4 problems, 4 pages Exam Two Solutions 22 October 2003
Problem 4 (3 parts, 23 points) More ways to implement state Part A (5 points) Consider a two bit counter with count enable (CE) and clear (CLR) displaying the flowing timing diagram. Identify the counter type.
CE
CLR
Clock
Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14
It’s a divide by 3 counter.
Part B (10 points) Suppose you are given the following incorrect implementation of a counter. Complete the timing diagram below by showing the outputs (O 0 and O 1 ) for clock cycles 7 through 14.
TE Out Clr
TE Out Clr
O 0
CLR O 1
CE
CE
CLR
Clock Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Part C (8 points) Design the max count detector needed for a divide by 25 counter. Label all inputs (counter outputs O 0 , O 1 , O 2 …). Don’t include unnecessary inputs.
A divide by 25 counter means Max Count = 25 - 1 = 24 = 11000 2. Only high outputs (O 3 and O 4 ) need to be tested.
O 3 O 4 Max Count
