Download Binary to Gray Code Conversion,Gate Level Modeling in Verilog (2)-Digital Logic Design-Lab Assignment and more Exercises Digital Logic Design and Programming in PDF only on Docsity!
Lab 3: Digital Logic Design Page 1
Department of Electrical Engineering
FacultyMember:_______________ Date ________________
Course/Section:____________ Semester:_____________
EE-241: Digital Logic Design
Lab4: Part (a): Binary to Gray Code Conversion
Lab4: Part (b): Gate-level Modeling in Verilog
Lab4: Part (a): Binary to Gray Code Conversion
Name Reg. No. Report
Marks /
Viva
Marks /
Total/
This Lab has been divided into two parts.
In first part you are required to design and implement a binary to gray and gray to binary code
converter. You will be cascading these two converters thus implementing a binary to gray coder
and decoder (gray to binary).
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Lab 3: Digital Logic Design Page 2
Pre-Lab Tasks: (To be done before coming to the lab)
- What do you mean by binary codes for the decimal digits? Give some examples and codes (tables) for the decimal digits. (1 Mark)
- What is a self-complimentary code? Name any two of them and show their complementary nature with examples. (1 Mark)
- In the lab you would be implementing a gray to binary and binary to gray code converter. Make a truth table for both the codes by filling in the following tables and Simplify the expressions for W,X,Y,Z in terms of A,B,C,D and vice versa.( Use backside of the page if necessary). Also give some applications in which gray code could be used. (4 Marks)
HINT:
Our inputs and outputs are of 4-bit each. You will have to make 4 K-Maps (Consider W as independent function of A,B,C,D, Make K-Map and simplify it). Arrive at the
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Lab 3: Digital Logic Design Page 4
A=
B=
C=
D=
- Draw the logic diagram for the above codes in the space provided below. (2 Marks)
Lab Tasks:
W
X
Y
Z
A
B
C
D
A
B
C
D
HINT:
Our inputs and outputs are of 4-bit each. You will have to make 4 K-Maps (Consider A as independent function of W,X,Y,Z. Make K-Map and simplify it). Arrive at the simplest expression for each output.
Binary
Gray
Binary
Lab 3: Digital Logic Design Page 5
Only the following gates are available to you for lab tasks.
Lab Task 1:
Implement the Binary to Gray Code Converter. Make the Schematic Diagram. Show the results to your Lab instructor / Assistant. Whatand how many gates did you use? Do not dispatch your hardware. You will need it in lab task 3. (3 Marks)
Lab Task 2:
Lab 3: Digital Logic Design Page 7
Design and simulate the gate-level model of the circuit you patched. Give the code in the space provided below. (5 marks)
Observations/Comments:
Note: - Viva Marks = 2.5 Marks
The lab marks will be condensed to 12.5 Marks.
