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An overview of computer memory, discussing the two main categories - primary and secondary memory, as well as specific types such as rom, ram, and cache. It explains the properties of each, including storage capacity, access time, and cost per bit, and the organization of main memory.
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Unit 2 Basic architecture 2.3 Types of memory Memory is an essential component of the computer system. It is used to store both instructions and data. It is used to store both instructions and data. Memory is made up of registers and the number of bits stored in a register is called memory word .Memory word is identified by an address .If processor uses 16 bit address , then there will be maximum of 216= 65536 memory addresses ranging from 0000H to FFFFH. There are various types of memory which can be classified in to two main groups i.e. Primary memory and Secondary memory.
Classification of memory
Main Memory: Every computer has a temporary storage area, which is built into the computer hardware, and in which instruction and data of a program are stored and executed by the CPU. This storage space is known as primary storage or main memory storage. Every storage unit of a computer system is characterized and evaluated based on the properties such as storage capacity, access time, and cost per bit of storage, volatile and random access.
1. Storage capacity: it is the amount of data, which can be stored in the storage unit. Main memory has less storage capacity. 2. Access time: this is the time required to locate and retrieve stored data from the storage unit, in response to a program instruction. Primary storage unit have faster
access time.
3. Cost per bit of storage: this refers to the cost of a storage unit for a given storage capacity. Primary storage units have higher cost per bit of storage. 4. Volatile. If the storage unit can retain the data stored in it, even when the power is turned off or interrupted, it is called non-volatile storage. On the other hand, if the data stored are lost, when the power is turned off or interrupted, it is called volatile storage. The non-volatile storage is desirable. 5. Random access: if the time taken to access a piece of data from the storage unit is independent of the location of the data in the storage unit, it is called a random access storage or random access memory (RAM). Each separate location of a RAM is as easy to access as any other location and takes the same amount of time.
Organization of main memory: A primary storage or main memory of a computer system is made up of several small storage areas, called locations or cells. Each of these locations can store a fixed number of bits, called word length of that particular memory. The given memory is divided into N words, where N generally is some power of 2. Each word or location has a built in and unique number assigned to it. This number is called the address of the location, and is used to identify the location. Each location can hold either a data item or an instruction. The addressed normally start at 0 and the highest address equals the number of words, which can be stored in the memory minus 1.
Types of main memory
RAM-random access memory(RW memory):
Random Access Memory called volatile and main memory of the computer system. It consist of some IC chips on the motherboard (circuit board). processor can read for and write into this memory .This memory is used for information that are likely to be altered such as writing program or receiving data. This memory is volatile i.e. the content will be lost if the power is turned off and commonly known as RAM, RAM are basically of two types. Read/write memory can be divided into static and dynamic categories. Static randomaccess memory (SRAM) retains the data, once written, without further manipulation so long as the source of power holds its value. SRAM is typically used for implementing the processor registers and cache memories. The bulk of main memory in a typical computer system, however, consists of dynamic random access memory (DRAM). DRAM is a complex memory device that uses a tiny capacitor to store a bit. A charged capacitor represents 1 bit. Since capacitors slowly lose their charge due to leakage, they must be refreshed periodically to replace the charges representing 1 bit. A typical refresh period is about 64 ms. Reading from DRAM involves testing to see if the corresponding bit cells are charged. Unfortunately, this test destroys the charges on the bit cells. Thus, DRAM is a destructive read memory. For proper operation, a read cycle is followed by a restore cycle. As a result, the DRAM cycle time, the actual time necessary between accesses, is typically about twice the read access time, which is the time necessary to retrieve a datum from the memory Several types of DRAM chips are available.
SRAM vs DRAM
A. Static RAM (SRAM) This memory is made up of flip flops and it stores bit as voltage. A single flip flop stores binary data either 1 or 0. Each flip flop is called storage cell. Each cell requires six transistors. Therefore, the memory chip has low density but high speed. This memory is more expensive and consumes more power. B. Dynamic RAM (DRAM) This memory is made up of MOS transistor gates and it stores the bit as charge. The advantage of DRAM are it has high density, low power consumption and cheaper than SRAM. But the bit information leaks therefore needs to be rewritten again every few milliseconds. It is called refreshing the memory and requires extra circuitry to do this. It is slower than SRAM.. FPM DRAMs Fast page-mode (FPM) DRAMs are an improvement over the previous generation DRAMs. FPM DRAMs exploit the fact that we access memory sequentially, most of the time. To know how this access pattern characteristic is exploited, we have to look at how the memory is organized. Internally, the memory is organized as a matrix of bits. For example, a 32-Mb memory could be organized as 8 K rows (i.e., 8192 since K = 1024) and 4-K columns. To access a bit, we have to supply a row address and a column address. In the FPM DRAM, a page represents part of the memory with the same row address. To access a page, we specify the row address only once; we can read the bits in the specified page by changing the column addresses. Since the row address is not changing, we save on the memory cycle time. EDO DRAMs Extended Data Output (EDO) DRAM is another type of FPM DRAM. It also exploits the fact that we access memory sequentially. However, it uses pipelining to speed up memory access. That is, it initiates the next request before the previous memory access is completed. A characteristic of pipelining inherited by EDO DRAMs is that single memory reference requests are not sped up. However, by overlapping multiple memory access requests, it improves the memory bandwidth. SDRAMs Both FPM DRAMs and EDO DRAMs are asynchronous in the sense that their data output is not synchronized to a clock. The synchronous DRAM (SDRAM) uses an external clock to synchronize the data output. This synchronization reduces delays and thereby improves the
reusable. The disadvantages are :(i) it must be taken out off circuit to erase it (ii). The entire chip must be erased (iii) the erasing process takes 15 to 20 minutes. D. Electrically Erasable PROM(EEPROM) :
It is functionally same as EPROM except that information can be altered by using electrical signal at the register level rather than erasing all the information. It is expensive compared to EPROM and flash and can be erased in 10 ms. E. Flash Memory:
It is variation of EPROM. The difference is that EPROM can be erased in register level but flash memory must be erased in register level but flash memory must be erased in its entirety or at block level. Cache memory: its memory between CPU and main memory. It is also called as buffer memory between CPU and main memory. It is used in temporary storage, data & instructing during processing. It is faster than main memory. It is commonly used for minimizing the memory processor speed mismatch.
2.4 INPUT/OUTPUT
Input/output (I/O) devices provide the means by which a computer system can interact with the outside world. An I/O device can be purely an input device (e.g., keyboard, mouse), purely
an output device (e.g., printer, display screen), or both an input and output device (e.g., disks). Here we present a brief overview of the I/O device interface. Chapters 14 and 15 provide more details on I/O interfaces. Computers use I/O devices (also called peripheral devices ) for two major purposes—to communicate with the outside world, and to store data. I/O devices such as printers, keyboards, and modems are used for communication purposes, and devices like disk drives are used for data storage. Regardless of the intended purpose of the I/O device, all communications with these devices must involve the systems bus. However, I/O devices are not directly connected to the system bus. Instead, there is usually an I/O controller that acts as an interface between the system and the I/O device. There are two main reasons f or using an I/O controller. First, different I/O devices exhibit different characteristics and, if these devices were connected directly, the processor would have to understand and respond appropriately to each I/O device. This would cause the processor to spend a lot of time interacting with I/O devices and spend less time executing user programs. If we use an I/O controller, this controller could provide the necessary low-level commands and data for proper operation of the associated I/O device. Often, for complex I/O devices such as disk drives, special I/O controller chips are available. The second reason for using an I/O controller is that the amount of electrical power used to send signals on the system bus is very low. This means that the cable connecting the I/O device has to be very short (a few centimeters at most). I/O controllers typically contain driver hardware to send current over long cables that connect the I/O devices. I/O controllers typically have three types of internal registers—a data register, a command register, and a status register—as shown in Figure 2.11. When the processor wants to interact with an I/O device, it communicates only with the associated I/O controller.