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ECE 126 Inverter Tutorial: Creating a Test Bench and Performing Transient Simulation - Pro, Lab Reports of Electrical and Electronics Engineering

George Washington University (GW)Electrical and Electronics Engineering

Prof. Thomas Farmer

This tutorial provides steps for university students to create a test bench for testing schematics and perform transient simulations using the spectres simulator in cadence. Students will learn to create a testbench, initialize the simulation environment, perform a transient analysis, save and plot simulation data, and save simulation states.

Typology: Lab Reports

Pre 2010

Uploaded on 02/25/2010

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ECE 126 – Inverter Tutorial: Test Bench Creation and Transient Simulation

Created for ECE 126 by Anis Nurashikin Nordin & Thomas Farmer

Tutorial adapted from:

http://www.ee.ttu.edu/ee/Cad ence/CommonDirectory/Final% 20Tutorials/DigitalCircuitSimulation usingVirtuoso.doc

Objectives:

• learn to create a test bench for testing schematics (steps 1-2)

• learn to perform a transient simulation using the SpectreS simulator (steps 3-7)

• learn to verify operation of schematic (steps 3-7)

• learn to save and recall simulator states (step 8)

Assumptions:

• UNIX environment is working (Lab 1)

• Schematic for inverter has been completed (Lab 1)

1. Login to workstation and start cadence

2. Creating the TestFixture (testbench)

• In the Library Manager, click on your “Digital” Library.

• From the Library Manager Menu choose: File



 New 



 Cellview...

• Fill it as shown below, to create a new cell called: inv_tb

• Click OK. A new Composer-Schematic window appears.

• Add the components below by using the same technique you used when creating the inverter

schematic in the previous lab.

• From the menu choose: Create->Instance (or simply press i )

• Using the component browser, “instance” the following parts onto your schematic, from the

following libiraries:

o vdd (Library: NCSU_analog_parts, Supply_Nets->vdd)

o gnd (Library: NCSU_analog_parts, Supply_Nets->gnd)

o DC Source (Library: NCSU_analog_parts, Voltage_Sources->vdc)

o pulsed voltage source (Library: NCSU_analog_parts, Voltage_Sources-

>vpulse)

o capacitor (Library: NCSU_analog_parts, R_L_C -> cap)

• Place them on your schematic in the arrangement shown in the figure below:

Discover Lab Reports of Electrical and Electronics Engineering George Washington University (GW)

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ECE 126 – Inverter Tutorial: Test Bench Creation and Transient Simulation

Created for ECE 126 by Anis Nurashikin Nordin & Thomas Farmer

Tutorial adapted from: http://www.ee.ttu.edu/ee/Cadence/CommonDirectory/Final%20Tutorials/DigitalCircuitSimulationusingVirtuoso.doc

Objectives:

learn to create a test bench for testing schematics (steps 1-2)
learn to perform a transient simulation using the SpectreS simulator (steps 3-7)
learn to verify operation of schematic (steps 3-7)
learn to save and recall simulator states (step 8)

Assumptions:

UNIX environment is working (Lab 1)
Schematic for inverter has been completed (Lab 1) **_1. Login to workstation and start cadence

Creating the TestFixture (testbench)_**

In the Library Manager, click on your “ Digital ” Library.
From the Library Manager Menu choose: File New Cellview...
Fill it as shown below, to create a new cell called: inv_tb
Click OK. A new Composer-Schematic window appears.
Add the components below by using the same technique you used when creating the inverter schematic in the previous lab.
From the menu choose: Create->Instance (or simply press i )
Using the component browser , “instance” the following parts onto your schematic, from the following libiraries:

o vdd ( Library : NCSU_analog_parts, Supply_Nets-> vdd ) o gnd ( Library : NCSU_analog_parts, Supply_Nets-> gnd ) o DC Source ( Library : NCSU_analog_parts, Voltage_Sources-> vdc ) o pulsed voltage source ( Library : NCSU_analog_parts, Voltage_Sources-

vpulse ) o capacitor ( Library : NCSU_analog_parts, R_L_C -> cap )

Place them on your schematic in the arrangement shown in the figure below:

The final component to instance is the inverter symbol you created in the last lab.

From the menu choose: Create->Instance (or simply press i )
In the component browser, choose the library: Digital
Select the “inv” part to instance, and you will be able to add your inverter's symbol to the schematic
Press after placing the inverter on your schematic.

3. Initializing the Simulation Environment

In the schematic window, from the menu select: Launch ADE L. Answer “ALWAYS” to any license upgrade pop-ups. In a few seconds, the Analog Artist Simulation window appears, as shown here. 4. Choosing a Simulation Engine and Model Libraries
In the Simulation window, select Setup Simulator/Directory/Host
Ensure the Simulator cyclic field is reading Spectre. Leave other fields to default.
In the simulation window, select Setup Model Libraries…
Ensure that the files shown below are in the list, if not, browse for the following files using the < …> icon:
Press OK to save your settings.

5. Performing a Transient Analysis

From the menu choose Analysis Choose...
The form appears.
Select the “ trans ” analysis
Note: trans analysis: This provides the transient output response of the circuit with respect to time. The user specifies the time period and the time variant input wave-form while the simulator calculates the output response.
Set stop time = 150u as shown in the figure (this will allow 3 pulses from our pulsed source).
Press OK 6. Saving and Plotting Simulation Data
We wish to select the output WIRE whose voltage we wish the simulator to record vs. time.
This is done from the simulator's menu by choosing:
Outputs To be Plotted Select on Schematic.
The schematic window is moved into the forefront. Now, “click” on the NET (aka wire) you wish to have plotted.
Click on the wire (aka NET), to the left of the inverter (the input net)
Then click on the wire to the right of the inverter (the output net)
Press < esc > to end “net selection” mode
Move your schematic window so that you can see the “simulation” window from before. You will notice in the “ Outputs ” region, the two NET's you selected will be listed (as in the figure below)
NOTE: your net name's may be different then the ones in this document.

8. Saving Simulation State

Once you have completed a complicated simulation, you may wish to “save” all of your simulation settings. From the simulator menu, choose : Session->Save State…
Give the “state” of the simulator a name that is meaningful like: inv_transient_simulation as in the graphic below:
Later, if you wish to recall the saved state, choose: Session->Load State… and you will be show all of the simulation states for this cell (inv_tb).

References

http://www.engr.sjsu.edu/~dparent/ICGROUP/CDS_1.pdf