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An in-depth exploration of parallel processing techniques, focusing on pipeline and vector processing. It delves into flynn's taxonomy, explaining single instruction single data (sisd), single instruction multiple data (simd), multiple instruction single data (misd), and multiple instruction multiple data (mimd). The document also discusses vector operations, matrix multiplication, memory interleaving, and various interconnection structures such as common bus, multiport memory, crossbar switch, multistage switching network, and hypercube system. It concludes with questions that could be asked in an exam related to these topics.
Typology: Schemes and Mind Maps
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Computer Organization & Architecture (COA)
Pipeline & Vector Processing 4 Parallel Processing (^) Parallel processing is a term used to denote a large class of techniques that are used to provide simultaneous data-processing tasks for the purpose of increasing the computational speed of a computer system. (^) Purpose of parallel processing is to speed up the computer processing capability and increase its throughput. (^) Throughput: The amount of processing that can be accomplished during a given interval of time. (^) Parallel processing comes under the following main topics: (^) Pipeline processing (^) Vector processing (^) Array processors
Pipeline & Vector Processing 5 (^) Figure below shows one possible way of separating the execution unit into eight functional units operating in parallel.
Pipeline & Vector Processing 7 Flynn's taxonomy Data Stream Instructio n Stream Single SISD SIMD Multiple Single Multiple MISD MIMD
Pipeline & Vector Processing 8 Single Instruction Single Data & Single Instruction Multiple Data Single Instruction Single Data (SISD) (^) SISD represents the organization of a single computer containing a control unit, a processor unit, and a memory unit. (^) Instructions are executed sequentially and the system may or may not have internal parallel processing capabilities. Single Instruction Multiple Data (SIMD) (^) SIMD represents an organization that includes many processing units under the supervision of a common control unit. (^) All processors receive the same instruction from the control unit but operate on different items of data.
Pipeline & Vector Processing 11 Vector Processing (^) In many science and engineering applications, the problems can be formulated in terms of vectors and matrices that lend themselves to vector processing. (^) Applications of Vector processing
Pipeline & Vector Processing 13 (^) This is a program for adding two vectors A and B of length 100 to produce a vector C. This is implemented in machine language by the following sequence of operations. (^) A computer capable of vector processing eliminates the overhead associated with the time it takes to fetch and execute the instructions in the program loop. It allows operations to be specified with a single vector instruction of the form. (^) The vector instruction includes the initial address of the operands, the length of the vectors, and the operation to be performed, all in one
Pipeline & Vector Processing 14 Vector Processing Matrix Multiplication (^) Matrix multiplication is one of the most computational intensive operations performed in computers with vector processors. (^) An n x m matrix of numbers has n rows and m columns and may be considered as constituting a set of n row vectors or a set of m column vectors. (^) Consider, for example, the multiplication of two 3x3 matrices A and B.
Pipeline & Vector Processing 16 Memory Interleaving (^) Pipeline and vector processors often require simultaneous access to memory from two or more sources. (^) An instruction pipeline may require the fetching of an instruction and an operand at the same time from two different segments. Similarly, an arithmetic pipeline usually requires two or more operands to enter the pipeline at the same time. (^) Instead of using two memory buses for simultaneous access, the memory can be partitioned into a number of modules connected to a common memory address and data buses. A memory module is a memory array together with its own address and data registers. Figure below shows a memory unit with four modules. Each memory array has its own address register AR and data register DR. (^) The modular system permits one module to initiate a memory access while other modules are in the process of reading or writing a word and each module can honor a memory request independent of the state of the other modules.
Pipeline & Vector Processing 17 Memory Interleaving AR Memory array DR AR Memory array DR AR Memory array DR AR Memory array DR Address bus Data bus
Section - 8
Pipeline & Vector Processing 20 Array Processors (^) An array processor is a processor that performs computations on large arrays of data. (^) Two different types of processors
1. Attached array processor: It is an auxiliary processor attached to a general-purpose computer. 2. SIMD array processor: It is a processor that has a single-instruction multiple-data organization. (^) Attached array processor:General- purpose computer Main memory Attached array processor Local memory Input-output interface High-speed memory to memory bus