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Implementation of Large Memory Chips
Consider a 4M x 4-bit chip which has a 22-bit addresses since 4M = 2^22.
Logically/Externally, we view a 4M x 4-bit memory as pictured below with: each memory word made up of four bits: b 3 b 2 b 1 b 0
b 3 b 2 b 1 b 0 Address
Decimal
22
.
.
.
When we want to read a word, we supply a 22-bit address, and receive the corresponding 4-bit word.
The register-file implementation (see handout), does not scale well for large memories for several reasons: the number of gates in the address decoder (and MUXs) grows exponentially with the number of bits in the address. lots of wires into/out of the memory chip for address, data, and control
These problems are solved by using square-array of bits and decoding the address in two parts (row then column number) eliminate MUX's by using tri-state buffers single-port RAM memory - data wires shared for reading and writing
Square Memory - 1
To help us see how the 4M x 4-bit memory gets mapped to the 2048 x 2048 x 4 memory array on the next page consider splitting memory into 2048 word blocks as shown below.
b 3 b 2 b 1 b 0 Address
Decimal
22
.
.
.
.
.
.
.
.
.
Binary Address
Row 0Row 0Row 0 Row 0
Row 1Row 1 Row 1Row 1
Row 2Row 2Row 2Row 2
Row 2047Row 2047Row 2047Row 2047
Row # Location in Row
Square Memory - 2
Implementing Large Memory with Smaller Chips
Consider for example, implementing 4M x 32 bits memory with 256KB x 1 bit chips. The 256KB x 1 chips are implemented as square arrays of 512 x 512.
We will use an two-dimensional array of the 256KB x 1 chips to implement the larger memory.
The number of chips per row would be 32 bits / 1 bit = 32 chips. The number of chips per column would be 4M / 256K = 2^22 / 2^18 = 2^4 = 16 chips per column.
The 22-bit address of the 4M x 32 bit memory would be split up as follows:
22-bit Address
4 bits chip row
18 bits
9 bits 9 bits
row # within chip
column # within chip
4-to- Decoder
512 x 512
512 x 512
512 x 512
512 x 512
512 x 512
512 x 512
512 x 512
512 x 512
512 x 512
chip
chip
chip
chip
chip
chip
chip
chip
chip
CS
CS
CS
CS
CS
CS
CS
CS
CS
Row 15
Row 0
Row 1
of Chips
of Chips
of Chips
Out
Out
Out
b 31 b 30 b 0
32 chips in a row
"CS" means Chip Select
(time-multiplexed)
Square Memory - 4
Figure 5.3. Typical 16 Mb DRAM (4M x 4)
Square Memory - 5
Figure 5.15. DDR SDRAM Road Timing
Double-data-rate SDRAM can send data twice per clock cycle
—Rising edge and falling edge
Square Memory - 7
