Addressing Modes - High Performance Computing - Lecture Slides, Slides of Computer Science

Download Addressing Modes - High Performance Computing - Lecture Slides and more Slides Computer Science in PDF only on Docsity!

High Performance Computing

Lecture 5

2

Addressing Modes: Operand in Memory

3. Register Indirect Addressing Mode

4. Base-Displacement Addressing Mode

5. Absolute Addressing Mode

6. Indexed Addressing Mode

Memory address of operand is calculated as sum of

contents of 2 registers

ADD R1, R2, (R3+R4)

4

Example: A RISC Instruction Set

 We must know a specific instruction set to

understand program code examples in the

remainder of this course

 Next: Details of a typical RISC instruction set

5

Example: A RISC Instruction Set (MIPS 1)

 Registers

 32 32b general purpose registers, R0..R

 R0 hardwired to value 0

 R31 implicitly used by some instructions

 “implicitly”: R31 will not be explicitly indicated as

an operand of the instruction

 Example: JALR R

 HI, LO: 2 other 32b registers

 Used implicitly by multiply and divide

instructions

 Example: MULT R1, R

7

MIPS I ISA: General Comments

 All instructions, registers are 32b in size

 Load-store architecture: the only instructions

that have memory operands are loads&stores

 Terminology

 Word: 32b

 Halfword: 16b

 Byte: 8b

 Displacements (for base-displacement mode)

and immediate values (for immediate mode)

are signed 16 bit quantities

8

Data Transfer Instructions

MFHI, MFLO, MFHI R1 R1  HI

MTHI, MTLO

Move

Store SB, SH, SW SB R2, - 8(R4) Mem[R4-8]  R

LB, LBU, LH, LW R2, 4(R3) R2  Mem[R3+4]

LHU, LW,

LUI

Load

Mnemonics Example Meaning

L: Load (data transfer from memory to a register)

S: Store (data transfer from a register to memory)

M: Move (between GPRs and HI/LO)

B: Byte (8b), H: Half (16b), W: Word (32b)

U: Unsigned; F: From; T: To, UI: Upper Immediate

10

LB and LBU

 Both load a byte from memory into the least

significant 8b of the destination register

 They differ in how they effect the rest of the

destination register

LB R1, 0(R2) LBU R1, 0(R2)

R

R

The byte from main memory

11

LB and LBU.

R

R

The byte from main memory

 Both load a byte from memory into the least

significant 8b of the destination register

 They differ in how they effect the rest of the

destination register

LB R1, 0(R2) LBU R1, 0(R2)

13

Integer Arithmetic/Logical Instructions

LO  lsw(R1*R2)

HI  msw(R1*R2)

MULT, DIV, MULT R1, R

MULTU, DIVU

Multiply,

Divide

AND, ANDI, ORI R1, R2, 0xF R1  R2|SE(0xF)

OR, ORI,

XOR, XORI,

NOR

Logical

R1  R2 + R

R1  R2 + 6

ADD R1, R2, R

ADDI R1, R2, 6

ADD, ADDU,

ADDI, ADDIU,

SUB, SUBU

Add,

Subtract

Mnemonics Example Meaning

Shift and Comparison instructions have been left out of this table

I: Immediate

LSW: Least Significant Word

SE: Sign Extension

14

Integer Arithmetic/Logical Instructions

LO  lsw(R1*R2)

HI  msw(R1*R2)

MULT, DIV, MULT R1, R

MULTU, DIVU

Multiply,

Divide

AND, ANDI, ORI R1, R2, 0xF R1  R2|SE(0xF)

OR, ORI,

XOR, XORI,

NOR

Logical

R1  R2 + R

R1  R2 + 6

ADD R1, R2, R

ADDI R1, R2, 6

ADD, ADDU,

ADDI, ADDIU,

SUB, SUBU

Add,

Subtract

Mnemonics Example Meaning

1. How do you get a constant value into a register?
2. How does the MULT instruction work?

16

Integer Arithmetic/Logical Instructions

LO  lsw(R1*R2)

HI  msw(R1*R2)

MULT, DIV, MULT R1, R

MULTU, DIVU

Multiply,

Divide

AND, ANDI, ORI R1, R2, 0xF R1  R2|SE(0xF)

OR, ORI,

XOR, XORI,

NOR

Logical

R1  R2 + R

R1  R2 + 6

ADD R1, R2, R

ADDI R1, R2, 6

ADD, ADDU,

ADDI, ADDIU,

SUB, SUBU

Add,

Subtract

Mnemonics Example Meaning

1. How do you get a constant value into a register?
2. How does the MULT instruction work?