Virtual Memory: Understanding DRAM, Page Size, and Address Translation in Memory Hierarchy, Study notes of Computer Architecture and Organization

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Lecture 14: Virtual Memory

Today: DRAM and Virtual memory basics (Sections 5.3-5.4)

DRAM Access

1M DRAM = 1024 x 1024 array of bits 10 row address bits arrive first Column decoder 10 column address bits arrive next Subset of bits returned to CPU 1024 bits are read out Row Access Strobe (RAS) Column Access Strobe (CAS)

Technology Trends

Improvements in technology (smaller devices)

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DRAM

capacities double every two years

Time to read data out of the array improves by only 5% every year

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high memory latency (the memory wall!)

Time to read data out of the column decoder improves by 10% every year

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influences bandwidth

Increasing Bandwidth

The column decoder has access to many bits of data – many sequential bits can be forwarded to the CPU without additional row accesses (fast page mode)

Each word is sent asynchronously to the CPU – every transfer entails overhead to synchronize with the controller – by introducing a clock, more than one word can be sent without increasing the overhead – synchronous DRAM

Virtual Memory

Processes deal with virtual memory – they have the illusion that a very large address space is available to them

There is only a limited amount of physical memory that is shared by all processes – a process places part of its virtual memory in this physical memory and the rest is stored on disk - Thanks to locality, disk access is likely to be uncommon - The hardware ensures that one process cannot access the memory of a different process

Address Translation

The virtual and physical memory are broken up into pages Virtual address 8KB page size page offset virtual page number Translated to physical page number Physical address 13

TLB^ •

Since the number of pages is very high, the page table capacity is too large to fit on chip

A translation lookaside buffer (TLB) caches the virtual^ to physical page number translation for recent accesses - A TLB miss requires us to access the page table, which^ may not even be found in the cache – two expensive^ memory look-ups to access one word of data! - A large page size can increase the coverage of the TLB^ and reduce the capacity of the page table, but also^ increases memory wastage

TLB and Cache •^

Is the cache indexed with virtual or physical address?

To index with a physical address, we will have to first^ look up the TLB, then the cache

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longer access time ¾ Multiple virtual addresses can map to the same^ physical address – can we ensure that these^ different virtual addresses will map to the same^ location in cache? Else, there will be two different^ copies of the same physical memory word

Does the tag array store virtual or physical addresses?

Since multiple virtual addresses can map to the same^ physical address, a virtual tag comparison can flag a^ miss even if the correct physical memory word is present

Cache and TLB Pipeline

TLB Virtual address Tag array Data array Physical tag comparion Virtual page number Virtual index Offset Physical page number Physical tag Virtually Indexed; Physically Tagged Cache

Superpages

If a program’s working set size is 16 MB and page size is 8KB, there are 2K frequently accessed pages – a 128-entry TLB will not suffice

By increasing page size to 128KB, TLB misses will be eliminated – disadvantage: memory wastage, increase in page fault penalty - Can we change page size at run-time? - Note that a single page has to be contiguous in physical memory

Ski Rental Problem^ •

Promoting a series of contiguous virtual pages into a superpage reduces TLB misses, but has a cost: copying physical memory into contiguous locations

Page usage statistics can determine if pages are good candidates for superpage promotion, but if cost of a TLB miss is x and cost of copying pages is Nx, when do you decide to form a superpage? - If ski rentals cost $20 and new skis cost $200, when do I decide to buy new skis?

If I rent 10 times and then buy skis, I’m guaranteed to^ not spend more than twice the optimal amount

Protection

The hardware and operating system must co-operate to ensure that different processes do not modify each other’s memory

The hardware provides special registers that can be read in user mode, but only modified by instrs in supervisor mode - A simple solution: the physical memory is divided between processes in contiguous chunks by the OS and the bounds are stored in special registers – the hardware checks every program access to ensure it is within bounds

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