Computer Architecture: MIPS Assembly Language Exercises and Solutions, Assignments of Linear Algebra

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Solutions

Chapter 2 Solutions S-

2.1 addi f, h, -5 (note, no subi)

add f, f, g

2.2 f = g + h + i

2.3 sub $t0, $s3, $s

add $t0, $s6, $t lw $t1, 16($t0) sw $t1, 32($s7)

2.4 B[g] = A[f] + A[1+f];

2.5 add $t0, $s6, $s

add $t1, $s7, $s lw $s0, 0($t0) lw $t0, 4($t0) add $t0, $t0, $s sw $t0, 0($t1)

2.6.1 temp = Array[0];

temp2 = Array[1]; Array[0] = Array[4]; Array[1] = temp; Array[4] = Array[3]; Array[3] = temp2;

2.6.2 lw $t0, 0($s6)

lw $t1, 4($s6) lw $t2, 16($s6) sw $t2, 0($s6) sw $t0, 4($s6) lw $t0, 12($s6) sw $t0, 16($s6) sw $t1, 12($s6)

Chapter 2 Solutions S-

2.14 r-type, add $s0, $s0, $s

2.15 i-type, 0xAD

2.16 r-type, sub $v1, $v1, $v0, 0x

2.17 i-type, lw $v0, 4($at), 0x8C

2.18.1 opcode would be 8 bits, rs, rt, rd fields would be 7 bits each

2.18.2 opcode would be 8 bits, rs and rt fields would be 7 bits each

2.18.3 more registers → more bits per instruction → could increase code size

more registers → less register spills → less instructions

more instructions → more appropriate instruction → decrease code size

more instructions → larger opcodes → larger code size

2.19.1 0xBABEFEF

2.19.2 0xAAAAAAA

2.19.3 0x

2.20 srl $t0, $t0, 11

sll $t0, $t0, 26 ori $t2, $0, 0x03ff sll $t2, $t2, 16 ori $t2, $t2, 0xffff and $t1, $t1, $t or $t1, $t1, $t

2.21 nor $t1, $t2, $t

2.22 lw $t3, 0($s1)

sll $t1, $t3, 4

2.23 $t2 = 3

2.24 jump: no, beq: no

S-6 Chapter 2 Solutions

2.25.1 i-type

2.25.2 addi $t2, $t2, – 1

beq $t2, $0, loop

2.26.2 i = 10;

do { B += 2;

i = i – 1;

} while ( i > 0)

2.26.3 5*N

2.27 addi $t0, $0, 0

beq $0, $0, TEST LOOP1: addi $t1, $0, 0 beq $0, $0, TEST LOOP2: add $t3, $t0, $t sll $t2, $t1, 4 add $t2, $t2, $s sw $t3, ($t2) addi $t1, $t1, 1 TEST2: slt $t2, $t1, $s bne $t2, $0, LOOP addi $t0, $t0, 1 TEST1: slt $t2, $t0, $s bne $t2, $0, LOOP

2.28 14 instructions to implement and 158 instructions executed

2.29 for (i=0; i<100; i++) {

result += MemArray[s0]; s0 = s0 + 4; }

S-8 Chapter 2 Solutions

2.34 f: addi $sp,$sp,-

sw $ra,8($sp) sw $s1,4($sp) sw $s0,0($sp) move $s1,$a move $s0,$a jal func move $a0,$v add $a1,$s0,$s jal func lw $ra,8($sp) lw $s1,4($sp) lw $s0,0($sp) addi $sp,$sp, jr $ra

2.35 We can use the tail-call optimization for the second call to func, but then

we must restore $ra, $s0, $s1, and $sp before that call. We save only one

instruction (jr $ra).

2.36 Register $ra is equal to the return address in the caller function, registers

$sp and $s3 have the same values they had when function f was called, and

register $t5 can have an arbitrary value. For register $t5, note that although

our function f does not modify it, function func is allowed to modify it so

we cannot assume anything about the of $t5 after function func has been

called.

2.37 MAIN: addi $sp, $sp, -

sw $ra, ($sp) add $t6, $0, 0x30 # ‘0’ add $t7, $0, 0x39 # ‘9’ add $s0, $0, $ add $t0, $a0, $ LOOP: lb $t1, ($t0) slt $t2, $t1, $t bne $t2, $0, DONE slt $t2, $t7, $t bne $t2, $0, DONE sub $t1, $t1, $t beq $s0, $0, FIRST mul $s0, $s0, 10 FIRST: add $s0, $s0, $t addi $t0, $t0, 1 j LOOP

Chapter 2 Solutions S-

DONE: add $v0, $s0, $ lw $ra, ($sp) addi $sp, $sp, 4 jr $ra

2.38 0x

2.39 Generally, all solutions are similar:

lui $t1, top_16_bits ori $t1, $t1, bottom_16_bits

2.40 No, jump can go up to 0x0FFFFFFC.

2.41 No, range is 0x604 + 0x1FFFC = 0x0002 0600 to 0x604 – 0x

= 0xFFFE 0604.

2.42 Yes, range is 0x1FFFF004 + 0x1FFFC = 0x2001F000 to 0x1FFFF

• 0x20000 = 1FFDF

2.43 trylk: li $t1,

ll $t0,0($a0) bnez $t0,trylk sc $t1,0($a0) beqz $t1,trylk lw $t2,0($a1) slt $t3,$t2,$a bnez $t3,skip sw $a2,0($a1) skip: sw $0,0($a0)

2.44 try: ll $t0,0($a1)

slt $t1,$t0,$a bnez $t1,skip mov $t0,$a sc $t0,0($a1) beqz $t0,try skip:

2.45 It is possible for one or both processors to complete this code without ever

reaching the SC instruction. If only one executes SC, it completes successfully. If

both reach SC, they do so in the same cycle, but one SC completes first and then

the other detects this and fails.