MIPS Assembly and Computer Architecture: Week 2, Study notes of Electrical and Electronics Engineering

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Computer Architecture and Assembly Language

Fall 06

Week 2 : ISA, MIPS Assembly

[Adapted from Dave Patterson’s UCB CS152 slides and

Mary Jane Irwin’s PSU CSE331 slides]

Assembly Language^ ‰

Language of the machine ‰ More primitive than higher level languages

e.g., no sophisticated control flow

‰^

Very restrictive

e.g., MIPS arithmetic instructions

‰^

We’ll be working with the MIPS instruction setarchitecture^ z

similar to other architectures developed since the 1980's z used by NEC, Nintendo, Silicon Graphics, Sony, … z 32-bit architecture

-^

32 bit data line and address line

-^ data and addresses are 32-bit

MIPS Arithmetic Instruction ‰^

MIPS assembly language arithmetic statement

add

$t0, $s1, $s

sub

$t0, $s1, $s

‰^

Each arithmetic instruction performs only oneoperation

‰^

Each arithmetic instruction specifies exactly threeoperands

destination

source

op

source

‰^

Those operands are contained in the datapath’sregister file (

$t0, $s1,$s

‰^

Operand order is fixed (destination first)

Fall 06

Compiling More Complex Statements ‰^

Assuming variable b is stored in register

$s

, c is

stored in

$s

, d is stored in

$s

and the result is to

be left in

$s

, and

$t

is a temporary register,

what is the assembler equivalent to the Cstatement

h = (b - c) + d

331 W02.

Fall 06

MIPS Register File

‰^

Operands of arithmetic instructions must be from alimited number of special locations contained inthe datapath’s register file^ z

Holds thirty-two 32-bit registers

-^ With two read ports and -^ One write port

Register File

src1 addrsrc2 addrdst addr write data

32 bits

src1data src2data

32 locations

32

5

32

(^5532)

Naming Conventions for Registers^0

$zero constant 0 1

$at reserved for assembler 2

$v0 expression evaluation & 3

$v1 function results 4

$a0 arguments 5

$a 6

$a 7

$a 8

$t0 temporary: caller saves

...

(callee can clobber)

15

$t

$s0 callee saves

...

(caller can clobber)

$s 24

$t

temporary (cont’d)

25

$t 26

$k0 reserved for OS kernel 27

$k 28

$gp pointer to global area 29

$sp stack pointer 30

$fp frame pointer 31

$ra return address

Accessing Memory ‰^ MIPS has two basic data transfer instructions foraccessing memory

lw $t0,

4($s3)

#load

word

from

memory

sw $t0,

8($s3)

#store

word

to

memory

‰^

The data transfer instruction must specify^ z

where in memory to read from (load) or write to (store) –memory address z where in the register file to write to (load) or read from(store) – register destination (source)

‰^

The memory address is formed by summing theconstant portion of the instruction and the contentsof the second register

Processor – Memory Interconnections ‰^ Memory is viewed as a large, single-dimensionarray, with an address ‰^ A memory address is an index into the array

Processor

Memory

read addr/write addr^ read datawrite data

(^322) Addressablelocations Q: what should be

the smallest addressable unit?

Fall 06

Byte Addresses ‰^

Since 8-bit bytes are so useful, most architecturesaddress individual bytes in memory^ memory: 2

32

bytes = 2

30

words

‰^

Therefore, the memory address of a word must bea multiple of 4 (alignment restriction)

Aligned

Not Aligned

Alignment restriction: requiresthat objects fall on address that ismultiple of their size.

Addressing Objects: Endianess and Alignment ‰^ Big Endian:

leftmost byte is word address

IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA

‰^

Little Endian:

rightmost byte is word address

Intel 80x86, DEC Vax, DEC Alpha (Windows NT)

lsb

little endian byte 0

msb

big endian byte 0

Compiling with Loads and Stores ‰^

Assuming variable b is stored in

$s

and that the

base address of integer array A is in

$s

, what is

the MIPS assembly code for the C statement

A[8] = A[2] - b

$s

$s

$s

... $s

.. .A[3]A[2]A[1]A[0]

Fall 06

Compiling with a Variable Array Index ‰^

Assuming A is an integer array whose base is inregister

$s

, and variables b, c, and i are in

$s

$s

, and

$s

, respectively, what is the MIPS

assembly code for the C statement

c = A[i] - b

Machine Language - Arithmetic Instruction ‰^

Instructions, like registers and words of data, arealso 32 bits long^ z

Example:

add

$t0,

$s1,

$s

z^

registers have numbers

$t0=$8,

$s1=$17,

$s2=$

‰^

Instruction Format:

Can you guess what the field names stand for?

op

rs^

rt^

rd^

shamt

funct

Fall 06

MIPS Instruction Fields

op

rs^

rt^

rd^

shamt

funct

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

= 32 bits

‰^

op

‰^

rs

‰^

rt

‰^

rd

‰^

shamt

‰^

funct