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Department of Electrical & Computer Engineering
COEN 212:
DIGITAL SYSTEMS DESIGN I
Lecture 9: Sequential Circuits
Latches and Flip-flops
Instructor: Dr. Reza Soleymani, Office: EV-5.125,
Telephone: 848-2424 ext.: 4103.
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Logic Circuits, latches and flip flops, Lecture notes of Digital Logic Design and Programming
The lecture document covers the introduction to sequential logic especially latches and flip flops which is the foundation of sequencing, counters and memory elements
Typology: Lecture notes
2020/2021
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Department of Electrical & Computer Engineering
COEN 212:
DIGITAL SYSTEMS DESIGN I
Lecture 9: Sequential Circuits
Latches and Flip-flops
Instructor: Dr. Reza Soleymani, Office: EV-5.125, Telephone: 848-2424 ext.: 4103.
Department of Electrical & Computer Engineering
Objectives of this lecture
โข In this lecture, we talk about:
โ Sequential Circuits.
โ Latches.
โ Flip-flops.
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Sequential Circuits:
- A typical Sequential Circuit:
- Example:
- State Table:
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Sequential Circuits:
- There are two types of sequential circuits:
- The synchronous circuits,
- The asynchronous circuits.
- In the synchronous circuits:
- state and also outputs change at discrete times dictated by a clock.
- In an asynchronous sequential circuit:
- the output of each gate is defined based on its input and gates delay. So, the state and outputs can change at any time.
- The problem with asynchronous circuits is the possibility of encountering instability due to feedback.
- In this course, we mainly consider Synchronous Sequential Circuits.
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Latches: SR-Latch with NAND
- SR latch implementation using NAND gates:
- Implementation: Operation:
- A Control or Enable input can be added.
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Latches: D-Latch
- D-Latch: avoids indeterminate state by making ๐ ๐ = ๐๐ โฒ
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Flip-flops
- There are two ways to implement edge-triggered flip-flops:
- isolate the input from the output. The output change only after control (clock) signal has been removed.
- make a flip-flop that only changes when level of its clock goes from 0 to 1 or from 1 to 0 and remains unchanged rest of the time.
- Implementing edge-triggered D flip-flop:
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D-Flip-flop
- Implementing D flip-flop using SR-Latch:
- as long as clk=0, ๐๐ = 1 and ๐ ๐ = 1 and output is unchanged.
- When clk goes to 1:
- if ๐ท๐ท = 0 makes ๐ ๐ = 0 and ๐๐ โฒ^ = 1 and ๐๐ = 0,
- if ๐ท๐ท = 1 the output of the lower most NAND will be 0 and ๐๐ = 0. ๐๐ = 1, ๐๐ โฒ^ = 0.
- Any further change in ๐ท๐ท while clk=1 will have no effect on the output.
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JK-Flip-flop
- Truth Table for D
- as a function of J, K and Q:
- The K-map for ๐ท๐ท
โข ๐ท๐ท = ๐ฝ๐ฝ๐๐ โฒ^ + ๐พ๐พ โฒ^ ๐๐
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JK-Flip-flop
- The Circuit Diagram for the J-K FF is:
- and the symbol is:
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T-Flip-flop
- For implementation using D-FF, we have:
โข and the circuit diagram is:
- T-FF could also be implemented using JK-FF
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Characteristic tables and equations:
โข Characteristic tables (or equations) describe the operation
of sequential circuits:
โข For a JK flip-flop the characteristic table is:
- And the Characteristic Function is:
๐๐ ๐ก๐ก + 1 = ๐ฝ๐ฝ๐๐ โฒ^ ๐ก๐ก + ๐พ๐พ โฒ^ ๐๐(๐ก๐ก)
where Q(t) and Q(t+1) are the state of the flip-flop, before and after the application of the clock signal.
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Flip-Flop with Direct Inputs:
- A flip-flop with a reset state:
- The symbol for D-FF with reset:
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Knowledge Check
- Question 1: In a JK FF Q=1, the input J=1, K=1 results in:
a) Q=1, b) Q=0, c) Qโ=0, d) undefined state
- Question 1: In a T FF Q=1, applying a four bit stream 1010 results in:
a) Q=1, b) Q=0, c) Qโ=0, d) Q=