Study with the several resources on Docsity
Earn points by helping other students or get them with a premium plan
Prepare for your exams
Study with the several resources on Docsity
Earn points to download
Earn points by helping other students or get them with a premium plan
Logic generation, Timing parameters, Structural RTL, Data path implementation, Control Signals, Fetch operation, Maximum clock are the topics professor discussed in class.
Typology: Slides
1 / 14
This page cannot be seen from the preview
Don't miss anything!
3
BUS<31..0>
3-to-8 Decoder 7 6 5 4 3 2 1 0
D Q
Q LCON
0
1
0
= 0
< 0
Bit <31> only
32
0 Never Branch Always Branch
Branch if zero
Branch if not zero
Branch if positive
Control signals for the br and brl instructions
Step RTL for br Control signals T0-T2 Instruction Fetch As before T3 CON cond(R[rc]); LCON, RCE, R2BUS T4 CON: PC R[rb] RBE, R2BUS, LPC (if CON=1)
Step RTL Control signals T0-T2 Instruction Fetch As before T3 CON cond(R[rc]); LCON, RCE, R2BUS T4 CON: R[ra] PC; RAE, BUS2R, PCout (if CON=1) T5 CON: PC R[rb]; RBE, R2BUS, LPC (if CON=1)
For the branch and link instructions:
Control signals for the shr instruction
Step RTN for shr Control signals
T0-T2 Instruction Fetch As before
T3 n<4..0> IR<4..0>; LN
T4 (N = 0) : (n<4..0> R[rc]<4..0>); LN(N=0), RCE, R2BUS
T5 C (Nα0) © R[rb]<31..N>; LC, SHR(N)
T6 R[ra] C; Cout, RAE, BUS2R
Hardwired
Control
Unit
…
…
output signals to various
parts of the processor
Block diagram of a Hardwired Control Unit
S.No Control
Signal
Boolean Equation
1 PCout T0+T3.(OP20+OP22)+T4.(OP16+..+OP19)
2 LMAR T0+T5.(OP28+OP29)
3 INC2 T
4 LC T3.(OP6+OP7+OP22..+OP25+OP14)+T4.(OP0+..OP3+OP +..+OP13+OP15+OP20+OP28+OP29)+T5.(OP22+OP23+O P16+..OP19)+T6.(OP4+OP5)
5 Cout T4.(OP6+OP7+OP24+OP25+OP22+OP23+OP14)+T5.(OP +..OP5+OP8+..+OP13+OP15+OP20+OP28+OP29)+T6.(OP 4+OP5+OP16+..+OP19)
6 LPC T1+T5.OP20+T6.CON.(OP16+..OP19)
7 MBRout T2+T7.(OP28+OP29)
8 LIR T
9 BUS2R T4.OP14+T5.(OP0+..+OP5+OP8+..OP11)+T7.OP
10 R2BUS T3.(OP0..+OP14)
11 LA T3.(OP0+..+OP5+OP8+..+OP11+OP20+OP22+OP28+OP29) +T4.(OP16+..+OP19)
Boolean Equations for some control signals
Op Op Op Op
PCout
PCout=T0+T3.(OP20+OP22)+T4.(OP16+..+OP19)
Example: Calculating the maximum clock
frequency for a circuit
Timing parameters:
Name Parameter FAST
Delays
VITESSE
Delays
Gate propagation time
tg 5 ns 150 ps
Bus propagation time (^) t b 5 ns^ 500 ps
Logic delay (^) t comb 14 ns^ ~400ps
Flip-flop propagation time
t 1 6 ns 440 ps
Flip-flop setup time (^) t su 2 ns^ 146 ps
Flip-flop hold time (^) t h 3 ns^ 104 ps
Flip-flop strobe width (^) t wmin 4 ns^ NA Docsity.com
For the FAST TTL gates, the minimum clock period can be
calculated as,
tmin=tg+tbp+t (^) comb+tl
=5+5+14+6=30ns+3ns(safety margin)=33ns
Hence the maximum clock frequency=1/(33x10 -9)=30 MHz
Similarly, for VITESSE gate array the minimum clock
period is,
tmin=tg+tbp+t (^) comb+tl
=150+500+400+440=1490 ps+safety margin=1.6ns
Maximum clock frequency=1/(1.6x10 -9)=625 MHz
Example: Calculating the maximum clock
frequency for a circuit
Step RTL
T0 MAR PC;
T3 A R[rb];
T4 R[ra] A - R[rc];
Structural RTL for the sub instruction
using the 2-bus data path implementation
Instruction Fetch
Instruction Execute
At the end of each sequence, the timing step generator is initialized to T
Step (^) RTN Control Signals
T0 MAR PC; PCout, LMAR, C=B;
T1 MBR M[MAR], PC PC + 4; PCout, INC4, LPC, MRead, MARout, LMBR; T2 IR MBR; MBRout, C=B, LIR;
T3 Instruction Execution
Control Signals for the Fetch operation
