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Randal E. Bryant

Carnegie Mellon University

CS:APP2e

CS:APP Chapter 4

Computer Architecture

Logic Design

http://csapp.cs.cmu.edu

Overview of Logic Design

Fundamental Hardware Requirements

 Communication

 How to get values from one place to another

 Computation

 Storage

Bits are Our Friends

 Everything expressed in terms of values 0 and 1

 Communication

 Low or high voltage on wire

 Computation

 Compute Boolean functions

 Storage

 Store bits of information

Computing with Logic Gates

 Outputs are Boolean functions of inputs

 Respond continuously to changes in inputs

 With some, small delay

a

b

out

a

b

out a^ out

out = a && b out = a || b out = !a

And Or Not

Voltage

Time

a

b

a && b

Rising Delay Falling Delay

Combinational Circuits

Acyclic Network of Logic Gates

 Continously responds to changes on primary inputs

 Primary outputs become (after some delay) Boolean

functions of primary inputs

Acyclic Network

Primary

Inputs

Primary

Outputs

Word Equality

 32-bit word size

 HCL representation

 Equality operation

 Generates Boolean value

b 31

Bit equal

a 31

eq 31

b 30

Bit equal

a 30

eq 30

b 1

Bit equal

a 1

eq 1

b 0

Bit equal

a 0

eq 0

Eq

=

B

A

Eq

Word-Level Representation

bool Eq = (A == B)

HCL Representation

Bit-Level Multiplexor

 Control signal s

 Data signals a and b

 Output a when s=1, b when s=

Bit MUX

b

s

a

out

bool out = (s&&a)||(!s&&b)

HCL Expression

HCL Word-Level Examples

 Find minimum of three

input words

 HCL case expression

 Final case guarantees

match

A

B MIN3^ Min

C

int Min3 = [

A < B && A < C : A;

B < A && B < C : B;

1 : C;

];

D

D

Out

s

s

MUX

D

D

 Select one of 4 inputs

based on two control

bits

 HCL case expression

 Simplify tests by

assuming sequential

matching

int Out4 = [

!s1&&!s0: D0;

!s1 : D1;

!s0 : D2;

1 : D3;

];

Minimum of 3 Words

4-Way Multiplexor

OF

ZF

CF

OF

ZF

CF

OF

ZF

CF

OF

ZF

CF

Arithmetic Logic Unit

 Combinational logic

 Continuously responding to inputs

 Control signal selects function computed

 Corresponding to 4 arithmetic/logical operations in Y

 Also computes values for condition codes

A

L

U

Y

X

X + Y

A

L

U

Y

X

X - Y

A

L

U

Y

X

X & Y

A

L

U

Y

X

X ^ Y

A

B

A

B

A

B

A

B

• 13 – CS:APP2e

0

1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Vin

V

V

0

1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Vin

Vin

V

Storing 1 Bit (cont.)

Bistable Element

Q+

Q–

q

!q

q = 0 or 1

V

in

V

1

V

2

V

in

V

1

V

2

V

in

= V

2

Stable 0

Stable 1

Metastable

Physical Analogy

0

1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Vin

V

V

0

1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Vin

Vin

V

Stable 0

Stable 1

Metastable

Stable left Stable right

Metastable

1-Bit Latch

D Latch

Q+

Q–

R

S

D

C

Data

Clock

Latching

Q+

Q–

R

S

D

C

Q+

Q–

R

S

D

C

d !d !d !d d

d d !d

Storing

Q+

Q–

R

S

D

C

Q+

Q–

R

S

D

C

d !d q

!q

!q

q 0

Transparent 1-Bit Latch

 When in latching mode, combinational propogation from D

to Q+ and Q–

 Value latched depends on value of D as C falls

Latching

Q+

Q–

R

S

D

C

Q+

Q–

R

S

D

C

d !d !d !d d

d d !d

C

D

Q+

Time

Changing D

Registers

 Stores word of data

 Different from program registers seen in assembly code

 Collection of edge-triggered latches

 Loads input on rising edge of clock

I O

Clock

D

C

Q+

D

C

Q+

D

C

Q+

D

C

Q+

D

C

Q+

D

C

Q+

D

C

Q+

D

C

Q+

i

7

i

6

i

5

i

4

i

3

i

2

i

1

i

0

o

7

o

6

o

5

o

4

o

3

o

2

o

1

o

0

Clock

Structure

Register Operation

 Stores data bits

 For most of time acts as barrier between input and output

 As clock rises, loads input

State = x

Rising

clock



Input = y Output = x

x



State = y

Output = y

y