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Main points of this past exam are: Logical Function, Memory Systems, Computer Engineering, Million Addresses, Column Number, Organization Approach, Number of Columns, Memory System, Instruction Formats, Datapath Elements
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4 problems, 4 pages Exam Three Solutions 28 November 2007
Problem 1 (3 parts, 30 points) Memory Systems
Part A (12 points) Consider a four Gbit DRAM chip organized as 128 million addresses of four byte words. Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate to form the memory address. Using the organization approach discussed in class, answer the following questions about the chip. Express all answers in decimal (not powers of two).
number of columns (^) sqrt(4G) = sqrt(2 32 ) = 2 16 = 64K number of words per column (^) 64K / 32 = 2^16 /2^5 = 2^11 = 2K column decoder required ( n to m ) (^) 16 to 64K type of mux required ( n to m ) (^) 2K to 1
number of address lines in column number (^16) number of address lines in column offset (^11)
Part B (10 points) Consider an eight megabyte memory system with 1 million addresses of 8 byte words using a 256 thousand address by 16 bit word memory DRAM chip.
word address lines for memory system (^) 1M address = 2^20 = 20 address lines
chips needed in one bank (^) 8 bytes / 2 byte = 4 chips/ bank banks for memory system (^) 1 M / 256K = 2^20 / 2^18 = 2^2 = 4 banks memory decoder required ( n to m ) (^) 2 to 4 DRAM chips required (^) 4 banks x 4 chips/bank = 16 chips
Part C (8 points) Design a 32 million address by 4 bit memory system with four 8M x 4 memory chips. Label all busses and indicate bit width. Assume R/W is connected and not shown here. Use a bank decoder if necessary.
8M x 4
D D D D
ADDR
CS
8M x 4
D D D D
ADDR
CS
8M x 4
D D D D
ADDR
CS
ADDR
25
MSEL
D D D D
8M x 4
D D D D
ADDR
CS
2 to 4
O O O EN O
23 23
23
23
23
2 A A
I I
A22:
4 problems, 4 pages Exam Three Solutions 28 November 2007
Problem 2 (parts, 24 points) Datapath Elements and Instruction Formats
Part A (6 points) Suppose the following inputs (in hexadecimal) are applied to the 32-bit barrel shifter used in the datapath. Determine the output (in hexadecimal). Assume the shift amount is drawn from the 16-bit immediate value.
Shift Type Shift Amount Input Value Output Value logical 0x000C^12345678
arithmetic 0x000C^ 4125C203^ 0004125C
rotate 0xFFF4^ FEDCBA98^ CBA98FED
Part B (8 points) For each bitwise logical function specification below, determine the LF code (in hexadecimal) to correctly program the logical unit.
X Y Out logical function LF
0 0 LF 0 X ⊕ Y 6
1 0 LF 1 X ⋅ Y 8
0 1 LF (^2) X 5
Part C (10 points) Consider the instruction set architecture below with fields containing zeros.
000 0000 0000 0000 0000 0000 0 0000 0000 0000 0000 opcode dest. reg. source 1 reg. immediate value What is the maximum number of opcodes? 128 What is the number of registers? (^256) What is the range of the signed immediate value? (^) ±64K
4 problems, 4 pages Exam Three Solutions 28 November 2007
Problem 4 (1 parts, 20 points) State Machines
Suppose you are designing a drought advisory state machine for the governor. It has two input signals:
S / R (which is 1 if the state of GA has had more mostly sunny days than rainy or cloudy days) and U / C (which is 1 if average water usage is above 100 gallons/person). There are three outputs:
Based on this state table, draw the state machine diagram that describes the drought advisory machine’s control logic. Use the state bubbles below, which are already labeled with mnemonic names. For maximum credit, merge redundant transitions into the most concise form. Show all required transitions and their input and output annotations.