Spring 2012 (Morrow)
1
1. (10 points) Memory Structures
A. For each of the below memory structures, express the memory size in bytes using the
appropriate prefix (K, M, G, etc).
a. 8589934592 x 2b
b. 32768 x 32b
c. 512 x 128b
d. 1048576 x 16b
B. For byte-wide memories of sizes 1KB, 1MB, 1GB, and 1TB, what is the number of memory
locations and the range of addresses for each device, all expressed in hexadecimal. How many
address bits are required for each range of addresses?
2. (15 points) Review of Memory Construction
A simple memory cell with bidirectional data can be constructed using just a D-FF and a tri-state
buffer. Using Quartus, you are to create such a memory cell, and then use it to construct an 8 x
4b memory. Implement your design by using the sample Quartus project linked on the course
web page as a starting point. Delete the file ece315_top.bdf, and set a new file sram_8x4.bdf to
be your top-level file. Create another new file mem_cell.bdf, and implement a single-bit memory
cell. Then use good hierarchical design techniques to create the logic for an 8x4b SRAM. You
may only use the following library parts in your design – input (pin), bidir (pin), dff, tri, and2,
and3, not. All parts can be found under the primitives tree in the Quartus Symbol window.
Note that this is an asynchronous design – there is no clock. Your circuit should have the
following external connections; A2, A1, A0, D3, D2, D1, D0, nWR, nRD. nWR and nRD are
active-low write and read signals, respectively. The data for a write operation should be stored
on the rising edge of nWR. D3-D0 are bidirectional data lines. It is assumed that you will never
drive the data lines while nRD is asserted. Use the minimum number of devices required to
complete the circuit.
Turn in paper copies of all BDF files.
3. (15 points) Review of Memory Operation
A. For the circuit you designed in #2 above, run a functional simulation to do the following -
1) write the 1’s-complement of the address of each memory location into each memory
location, starting at address 0
2) read the value of each memory location, starting at address 7
Make the read and write signals active for 10ns during each operation, and allow 10ns between
each transfer with both nRd and nWR negated. Turn in a paper copy of your simulation trace.
Annotate your trace to clearly indicate what is happening.
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