Machine Organization and Assembly Language - Study Guide | CISC 360, Study notes of Computer Architecture and Organization

Download Machine Organization and Assembly Language - Study Guide | CISC 360 and more Study notes Computer Architecture and Organization in PDF only on Docsity!

CISC260 Machine Organization

and Assembly Language

Memory hierarchy

And

Cache

Direct mapped

Example: run the code on 2-sets four-word block cache which is initially empty

What locality is being used? What is the miss rate?

Suppose a computer system has a memory organization with only two levels of hierarchy, a cache and main memory, with access times and miss rates given as follows:

Access Time Miss rate (Cycles) Cache 1 10% Main Memory 100 0%

What is the average memory access time?

Solution: The average memory access time is 1 + 0.1 (100) = 11 cycles.

Memory Performance Impact on Performance

• Suppose a processor executes at
  • ideal CPI = 1.
  • 50% arith/logic, 30% ld/st, 20% control

and that 10% of data

memory operations miss with a 50 cycle miss penalty

• CPI = ideal CPI + average stalls per instruction =

1.1(cycle) + ( 0.30 (datamemops/instr)

x 0.10 (miss/datamemop) x 50 (cycle/miss) )

= 1.1 cycle + 1.5 cycle = 2.

so 58% of the time the processor is stalled waiting for memory!

• A 1% instruction miss rate would add an additional 0.5 to the

CPI!

In a Row-major arrangement, for example, the elements for a 3x3 matrix A are stored in memory like

A[0,0], A[0, 1], A[0, 2], A[1, 0], A[1, 1], A[1, 2], A[2, 0], A[2, 1], A[2, 2]

In a Column-major arrangement, for example, the elements for a 3x3 matrix A are stored in memory like

A[0,0], A[1, 0], A[2, 0], A[0, 1], A[1, 1], A[2, 1], A[0, 2], A[1, 2], A[2, 2]

Therefore, the order of looping through the matrix indices is essential for spatial locality.

Sum = 0; for(i=0; i<2; i++) for(j=0; j<2; j++) sum += A[i,j];

Locality

Sum = 0; for(j=0; j<2; j++) for(i=0; i<2; i++) sum += A[i,j];

No locality

Advanced issues (CISC 360)

• Cope with cache block conflicts: multi-way associative cache
• write data