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EE221: Digital Logic Design - Lab 9: Magnitude Comparator, Lecture notes of Computer Science

Alagappa UniversityComputer Science

This has the design along with the truth tables of a magnitude comparator and circuit diagram. the pin configuration is also given.

Typology: Lecture notes

2019/2020

Uploaded on 01/15/2020

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EE221: Digital Logic Design Page 1
Department of Electrical Engineering
Faculty Member:__Nasir Mahmood___ Dated: ___3-12-19____
Semester:___3rd_____ Section: _______B______
EE-221: Digital Logic Design
Lab 9: Magnitude Comparator
PLO4/CLO4
PLO4/CLO4
PLO5/CLO5
PLO8/CLO6
PLO9/CLO7
Name
Reg. No
Viva / Lab
Performanc
e
Analysis
of data in
Lab Report
Modern
Tool Usage
Ethics and
Safety
Individual
and Team
Work
Total
marks
Obtained
5 Marks
5 Marks
5 Marks
5 Marks
5 Marks
25 Marks
Maryam Mahmood
257913
Rushna Shah
249747
Group No.: 5
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff

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Download EE221: Digital Logic Design - Lab 9: Magnitude Comparator and more Lecture notes Computer Science in PDF only on Docsity!

Department of Electrical Engineering

Faculty Member:Nasir Mahmood_ Dated: ___ 3 - 12 - 19 ____

Semester:___3rd_____ Section: _______B______

EE-221: Digital Logic Design

Lab 9: Magnitude Comparator PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO Name Reg. No Viva / Lab Performanc e Analysis of data in Lab Report Modern Tool Usage Ethics and Safety Individual and Team Work Total marks Obtained 5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks Maryam Mahmood 257913 Rushna Shah 249747

Group No.: 5

Lab 9 : Magnitude Comparator

Lab Instructions

 This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab

Viva session.

 The lab report will be uploaded on LMS three days before scheduled lab date. The

students will get hard copy of lab report, complete the Pre-lab task before coming to

the lab and deposit it with teacher/lab engineer for necessary evaluation.

 The students will start lab task and demonstrate design steps separately for step-

wise evaluation( course instructor/lab engineer will sign each step after ascertaining

functional verification)

 Remember that a neat logic diagram with pins numbered coupled with nicely

patched circuit will simplify trouble-shooting process.

 After the lab, students are expected to unwire the circuit and deposit back

components before leaving.

 The students will complete lab task and submit complete report to Lab Engineer

before leaving lab.

 There are related questions at the end of this activity. Give complete answers.

This Lab Activity has been designed to familiarize students with design and working of

combinational circuits using basic logic gates.

Objectives:

 Design and Implementation of 2-bit magnitude comparator using classical design method

learned in the class.

 Design of a 4-bit magnitude comparator using a 4-bit adder IC and logic gates

 Verification of 4 bit comparator IC

 Dataflow modeling in Verilog HDL

  1. Simplify the functions E, G and L and give their Logic diagrams.

Lab Tasks: 3 marks

  1. Implement the 2-bit Comparator circuit you arrived in your Pre-lab Task. Give the Complete circuit schematic diagram here again.
  1. A magnitude comparator can be constructed by using a subtractor and an additional combinational circuit. This is done with a combinational circuit that has 5 inputs S1, S2, S3, S4, and Co, and three outputs E, G, L as shown below. E = 1 if A=B i.e. when S = 0000, L = 1 if A B i.e. when Co = 1 and S ≠ 0000. Design and construct this additional combinational circuit using minimum number of gates. You have to design this part

G

L

E

A 3 , B 3 A 2 , B 2 A 1 , B 1 A 0 , B 0 A>B AB A<B A=B

A 3 = B 3 A 2 = B 2 A 1 = B 1 A 0 = B 0 0 0 0 1 1 0 ii i www.flintgroups.com

  • A 3 > B 3 X X X X X X
  • A 3 < B 3 X X X X X X
  • A 3 = B 3 A 2 > B 2 X X X X X
  • A 3 = B 3 A 2 < B 2 X X X X X
  • A 3 = B 3 A 2 = B 2 A 1 > B 1 X X X X
  • A 3 = B 3 A 2 = B 2 A 1 < B 1 X X X X
  • A 3 = B 3 A 2 = B 2 A 1 = B 1 A 0 > B 0 X X X
  • A 3 = B 3 A 2 = B 2 A 1 = B 1 A 0 < B 0 X X X
  • A 3 = B 3 A 2 = B 2 A 1 = B 1 A 0 = B
  • A 3 = B 3 A 2 = B 2 A 1 = B 1 A 0 = B
  • A 3 = B 3 A 2 = B 2 A 1 = B 1 A 0 = B
  • A 3 = B 3 A 2 = B 2 A 1 = B 1 A 0 = B 0 X X
  • A 3 = B 3 A 2 = B 2 A 1 = B 1 A 0 = B