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Department of Electrical Engineering
Faculty Member: Ma’am Rabbiya Khalid Dated: 06-05-
Semester: 2nd Section: ___B_____________
EE-221: Digital Logic Design
Lab 10: Magnitude Comparator PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO Name Reg. No Viva / Lab Performanc e Analysis of data in Lab Report Modern Tool Usage Ethics and Safety Individual and Team Work Total marks Obtained 5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks Muhammad Ahmad^282660 Muhammad Uzair Hasnain
Lab 10: Magnitude Comparator
Group No.:
Lab Instructions
This lab activity comprises three parts, namely Pre-lab, Lab tasks, and
Post-Lab Viva session.
The lab report will be uploaded on LMS three days before scheduled lab
date. The students will get hard copy of lab report, complete the Pre-lab
task before coming to the lab and deposit it with teacher/lab engineer for
necessary evaluation.
The students will start lab task and demonstrate design steps separately
for step-wise evaluation( course instructor/lab engineer will sign each step
after ascertaining functional verification)
Remember that a neat logic diagram with pins numbered coupled with
nicely patched circuit will simplify trouble-shooting process.
After the lab, students are expected to unwire the circuit and deposit back
components before leaving.
The students will complete lab task and submit complete report to Lab
Engineer before leaving lab.
There are related questions at the end of this activity. Give complete
answers.
This Lab Activity has been designed to familiarize students with design and working of
combinational circuits using basic logic gates.
Objectives:
Design and Implementation of 2-bit magnitude comparator using classical designmethod
learned in the class.
Design of a 4-bit magnitude comparator using a 4-bit adder IC and logic gates
Verification of 4 bit comparator IC
Dataflow modeling in Verilog HDL
- Design a 2-bit magnitude comparator. The Block diagram is shown below. a) List the truth table.
Inputs Outputs
A1 A0 B1 B0 E (A=B) G (A>B) L (A<B)
b) Simplify each of the functions E, G and L and give their logic diagrams (Hint: If you can simplify any two, you can get the third one. How it is possible?)
Fe=(A0’B0’+A0B0)(A1’B1’+A1B1)
Fg=A0B0’(B1’+A1)+A1B1’
Fl=A1’B1+A0’B0(A1’+B1)
Lab Tasks: 3 marks
Design and construct this additional combinational circuit using minimum number of Answer: According the given problem we have made the following simplified expressions and these expressions are as follows: E=(^ S ¿¿^0 +^ S 1 +^ S 2 +^ S 3 ) ¿
= S 0
¿
S 1
¿
S 2
¿
S 3
¿
G= C 0
¿
L= E
¿
L
¿ = C 0 ( S^ ¿¿^0 +^ S 1 +^ S 2 +^ S 3 )¿ The simplifies circuit so formed is given as You have to design this part
G
L
E
- Write verilog code of 2 bit comparator using dataflow modeling. (3 marks - Modern tool usage) CODE: module lab10(E,L,G,A0,A1,B0,B1); input A0,A1,B0,B1; output E,G,L; assign E = ~(A1^B1)&~(A0&B0); assign G = (A1&B1)|((A0&B0)&(A1|~B1)); assign L = (~A1&B1)|((~A0&B0)&(~A1|B1)); endmodule module test10: reg A1,A0,B1,B wire E,G,L; initial begin #100 A1=1'b0;A0=1'b0;B1=1'b0;B0=1'b0; #100 A1=1'b0;A0=1'b0;B1=1'b0;B0=1'b1; #100 A1=1'b0;A0=1'b0;B1=1'b1;B0=1'b0; #100 A1=1'b0;A0=1'b0;B1=1'b1;B0=1'b1; #100 A1=1'b0;A0=1'b1;B1=1'b0;B0=1'b0; #100 A1=1'b0;A0=1'b1;B1=1'b0;B0=1'b1; #100 A1=1'b0;A0=1'b1;B1=1'b1;B0=1'b0; #100 A1=1'b0;A0=1'b1;B1=1'b1;B0=1'b1; #100 A1=1'b1;A0=1'b0;B1=1'b0;B0=1'b0; #100 A1=1'b1;A0=1'b0;B1=1'b0;B0=1'b1; #100 A1=1'b1;A0=1'b0;B1=1'b1;B0=1'b0; #100 A1=1'b1;A0=1'b0;B1=1'b1;B0=1'b1; #100 A1=1'b1;A0=1'b1;B1=1'b0;B0=1'b0; #100 A1=1'b1;A0=1'b1;B1=1'b0;B0=1'b1; #100 A1=1'b1;A0=1'b1;B1=1'b1;B0=1'b0; #100 A1=1'b1;A0=1'b1;B1=1'b1;B0=1'b1; end endmodule
