Main Mem.. CSE 471 Autumn 01 1
Main Memory
• The last level in the cache – main memory hierarchy is the
main memory made of DRAM chips
• DRAM parameters (memory latency at the DRAM level):
–Access time: time between the read is requested and the desired
word arrives
–Cycle time: minimum time between requests to memory (cycle
time > access time because need for stabilization of address lines)
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DRAM’s
•Address lines split into row and column a ddresses. A read
operation consists of:
–RAS (Row access strobe)
–CAS (Column access strobe)
–If device has been precharged, access time = RAS + CAS
–If not, have to add precharge time
–RAS, CAS, and Precharge are of the same order of magnitude
–In DRAM, data needs to be written back aft er a read, hence cycle
time > access time
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DRAM
array
Row
address
Column
address
page
Page buffer
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DRAM and SRAM
•D stands for “dynamic”
–Each bit is single transistor (plus capacitor; hence the need to
rewrite info after a read).
–Needs to be recharged periodically. Hence re freshing. All bits in a
row can be refreshed concurrently (just read t he row).
–For each row it takes RAS time to refresh (c an lead to up to 5%
loss in performance).
•S stands for “static”
–Uses 6 transistors/bit (some use 4). No refresh a nd no need to write
after read (i.e., information is not lost by reading; ve ry much like a
F/F in a register).
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DRAM vs. SRAM
•Cycle time of SRAM 10 to 20 times faster than DRAM
•For same technology, capacity of DRAM 5 to 10 times that
of SRAM
•Hence
–Main memory is DRAM
–On-chip caches are SRAM
–Off-chip caches (it depends)
•DRAM growth
–Capacity: Factor of 4 every 3 years (60% per ye ar)
–Cycle time. Improvement of 20% per genera tion (7% per year)
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How to Improve Main Memory Bandwidth
•It’s easier to improve on bandwidth than o n latency
•Sending address: can’t be improved (and this is latency)
–Although split-transaction bus allows some ove rlap
•Make memory wider (assume monolithic m emory)
–Sending one address, yields transfer of more tha n one word if the
bus width allows it (and it does nowadays)
–But less modularity (buy bigger increments of memory)
