Memory Devices, Slides of Design

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Memory Devices

Small: Register file (group of numbered registers)

Medium: SRAM (Static Random Access Memory)

Large: DRAM (Dynamic Random Access Memory)

Future?

ALU

Processor: Data Path Components

Registers Memory

Instruction Fetch and Decode

SRAM read port: data out Large register files are impractical. Big MUX = significant gate delay. Large memories use a shared output line. No central gates/MUX to choose output!

Wired ORs Danger, Will Robinson! (don't try this at home/in the lab, kids)

SRAM cell one option

D Q

C

D Latch

Q

Enable

Data In

Clock

Data Out

Tristate Buffer

SRAM write port: FIGURE C.9.3 The basic structure of a 4 × 2 SRAM consists of a decoder that selects which pair of cells to activate latch D C Enable Q D 0 2-to- decoder Write enable Din[1] latch D C Enable Q D Din[1] Dout[1] Dout[0] latch D C Enable Q D 1 latch D C Enable Q D latch D C Enable Q D 2 latch D C Enable Q D latch D C Enable Q D 3 latch D C Enable Q D Address Write enable Address

Dout[1] D

out[0]

Din[1] Din[0]

to

4 decoder

0 1 2 3 Write enable Address select

Din[i]

latch D C Enable Q D Din[1] latch D C Enable Q D Din[1] latch D C Enable Q D latch D C Enable Q D D D D D

Data out:

Data in:

Dout[i]

Selecting location 1101 4 to 16 decoder data out

4 - bit address

Another organization of a 16 x 4 SRAM top 2 bits address Mux Mux Mux (^) Mux bottom 2 bits address Split-level row/column addressing = physical multidimensional array! (row) (column) 2 to 4 decoder Notice the smaller decoder... how does this affect timing?

Selecting location 1101 top 2 bits address Mux Mux Mux (^) Mux bottom 2 bits address (row) (column) 2 to 4 decoder Nibbles "striped" across 4 smaller memories.

What value does location 1010 hold? 0 1 1 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0 1 1 1 1 1 Mux Mux Mux (^) Mux 2 to 4 decoder

Dynamic RAM = DRAM DRAM stores bit as charge on capacitor:

• 1 transistor accesses stored charge.
• requires periodic refresh = read-write (dynamic power) SRAM stores bit on pair of inverting gates:
• several transistors
• requires continuous (static) power. Word line Pass transistor Capacitor Bit line FIGURE C.9.5 A single-transistor DRAM cell contains a capacitor th contents and a transistor used to access the cell. Row decoder 11-to- 2048! arra

DRAM design FIGURE C.9.5 A single-transistor DRAM cell contains a capacitor that stores the ce contents and a transistor used to access the cell. Address[10–0] Row decoder 11-to- 2048! 2048 array Column latches Mux Dout FIGURE C.9.6 A 4M × 1 DRAM is built with a 2048 × 2048 array. The row access uses 11 bits select a row, which is then latched in 2048 1-bit latches. A multiplexor chooses the output bit from these 20 Accesses entire row, stores in column latches. Mainly used for refreshing entire row at a time. Accessing other columns in same row again cheaper...? Single set of address lines, time-shared for row address, column address. 18 (one option)

Reading bit at address 101011

1. Select row 3 to 8 row decoder Mux Column latches 3 - bit address

Data out

Reading bit at address 101011

2. Copy row to latches 3 to 8 row decoder Mux Column latches Row is fading! 3 - bit address

Data out