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Main points of this exam paper are: Memory Address, Block Size, Maximum File, File Size, Mapped Cache, Direct Mapped, Lru Replacement, Replacement Policy, Address Translation, Memory Address
Typology: Exams
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University of California, Berkeley College of Engineering Computer Science Division – EECS
Fall 1999 Anthony D. Joseph
November 10, 1999 CS162 Operating Systems
Your Name:
SID:
Circle the letters of your CS162 login (1 per line):
a b c d e f g h i j k l m n o p q r s t u v w x y z
a b c d e f g h i j k l m n o p q r s t u v w x y z
TA Name / Section:
This is a closed book examination. You have two hours to answer as many questions as possible. The number in parentheses at the beginning of each question indicates the number of points given to the question; there are 100 points in all. You should read all of the questions before starting the exam, as some of the questions are substantially more time consuming.
Write all of your answers directly on this paper. Make your answers as concise as possible. If there is something in a question that you believe is open to interpretation, then please ask us about it!
Problem Possible Score 1 12
Total 100
Why:
b. A direct mapped cache can sometimes have a higher hit rate than a fully associative cache with an LRU replacement policy (on the same reference pattern).
Why:
c. Virtual memory address translation is useful even if the total size of virtual memory (summed over all programs) is guaranteed to be smaller than physical memory.
Why:
b. (14 points) Specify how you implement a write-behind policy. Assume a write- behind occurs every 30 seconds. Assume that a file is only opened by one process at a time. You do not have to show how you would modify the read operation.
i) List the data structures, methods, or classes you would either use or modify:
ii) Provide the algorithm for the policy in pseudocode form. Your solution should take less than twenty lines of pseudocode. No optimizations are necessary, however your solution should handle any synchronization issues. You can use any Nachos functions that you would need (if they’re not standard, or are from your own project phases, explain their operation).
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b. (5 points) The HAL Junior price sheet looks like this:
Item Specs Price Larger TLB Reduces the probability of a TLB miss to 0.05. Assume that there is sufficient memory that the page fault rate is unaffected.
Hard Disk-Drive II Transfers a page in 8 milliseconds $ 8 MByte more memory
Makes probability of a page fault, given a TLB miss, 0.
Suppose your friend has $1000. Which components should they buy if they want to maximize the performance of their HAL Junior? State the reasoning behind your choices.
No Credit – Problem X: (000000000000 points)
The news is not very good for Bill Gates. On Friday, the judge in the antitrust trial of Microsoft ruled that the software company has monopoly power in PC operating systems and that it has used that power to crush potential threats from competitors.
For each of the following page replacement algorithms, sketch a graph showing the paging behavior. Assume that the program has been running for several iterations through the array. The y-axis of each graph is the number of page faults per referenced page , varying from 0 to 1; the x-axis is the size of the array being scanned, varying from smaller than physical memory to much larger than physical memory. Label any interesting points on the graph on both the x and y axes.
a. FIFO
Size of array
Number of page faults per referenced page
b. LRU
Size of array
Number of page faults per referenced page
c. MIN
Size of array
Number of page faults per referenced page