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University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh3:30-5pm e141@eecs
EECS 141: SPRING 97 — FINAL
For all problems, you can assume the following transistor parameters:
NMOS:
VTn = 0.75V, k’n = 20 μA/V^2 , λ = 0, γ = 0.5 V1/2, 2ΦF = -0.6V, LD = 0.15 μm
PMOS:
VTp = -0.75V, k’p = 7 μA/V^2 , λ = 0, γ = 0.5 V1/2, 2ΦF = -0.6V, LD = 0.15 μm
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Problem 1:
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Problem 6:
Have a great summer!
Problem 1: Memory Design
Designer Dilbert is asked to design a low power ROM. He decides that a NAND structure with 16 cells per column is probably the appropriate choice. He finally comes up with the structure shown below. The following properties of the cell are known: size: 6μm x 6μm, (W/L) = (1.8/1.2). Source and drain overlap capacitance of 3 fF, gate capacitance of 8 fF, source and drain diffusion capacitance = 10 fF, bitline/capacitance per cell = 1 fF.
a. Evaluate if Dilbert is correct in his assumption that this structure is indeed low power. Give the pro and con arguments.
b. Determine the size of the pull-up transistor such that the maximum voltage swing at BL equals 0.5 V. You may ignore body effect in this problem.
WL[0]
WL[1]
WL[2]
WL[15]
BL
V (^) DD = 3.3 V
Pull-Up
1.8/1.
W/L=
f. Suddenly, Dilbert gets a troke of genius. He figures out that by using a special encoding on the stored data he can save some more power (see Figure below). The scheme works as
follows: assume that for a given wordline WL [i] the number of stored 1’s is larger than the number of 0’s. In that case the data is left unchanged and INV [i] is set to 0. In case the number of stored 0’s is larger than the number of 1’s, all data in the memory is inversed and bit INV [i] is set to 1. The INV bits are stored as an extra column in the memory. Explain why this approach can help to save power.
g. Determine the logic function that should be performed by the box with the question mark in the Figure so that the correct data is retrieved from the memory.
Figure: Example of encoding scheme (for 6 x 6 ROM)
(^1 1 1 1 1 1 ) 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11
0 0 0
0 0 0 0
PROBLEM 2: Arithmetic
It is your task to implement an arithmetic circuit that performs the following task: x = ( a + b ) ≥ c , where a , b , and c are all N -bit two’s complement numbers and x is a one bit result!
a. Draw the block diagram of your datapath using RIPPLE-BASED LOGIC. The block diagram should contain the basic cells you are using and their interconnections (in the style of Figure 7.31 in the text book). For each cell, describe the logic function.
b. Determine the delay of the datapath as a function of N and the delay parameters of the basic cells.
PROBLEM 3: Timing
Consider the following simple processor, consisting of a pipelined data path and a finite-state machine based controller. RF, PR, and IR denote edge-triggered flip-flops, while DP1, DP2 and FSM denote logic modules. Minimum and maximum delays of the modules are shown in the table next to the Figure. You may ignore the delay of the inter- connect as well as the delays of the registers. The δ’s at the clock inputs of the registers denote the absolute skew between the clock source and the register.
a. Write down the necessary constraints on the clock skews to avoid race conditions. Do not solve!.
b. Derive the constraints on the clock period in the presence of skew. Do not solve.
RF PR
δ 1 δ 2
Figure : Simple Processor
DP1 DP
FSM
δ 3 IR
min delay max delay DP DP FSM
c. Assuming that you are free to set the values of the skews, determine the minimum pos- sible clock period..
d. Determine the values of the skews for which this minimum period is achieved.
e. Propose a revised architecture that would reduce the clock period (changing circuit style is not an option ...). Explain why. Discuss also the disadvantages of your approach.
Tmin
b. Assume next that the wire is implemented in copper, for which the resistance is that low that it may be ignored. Which driver is now the better choice? Compute for both cases at what point 90%of the final voltage is reached. Explain your result.
c. Answer yes or no the the following questions related to interconnect:
- Electromigration problems can be resolved by increasing the wire width.
- When running into transmission line effects, it helps to replace the wire material by a wire material with lower sheet resistance.
- Crosstalk between wires can have an adverse effect on speed performance.
- Ldi/dt effects can be cured by increasing the sizes of the transistors in the drivers for the output pads.
t90% (Driver 1) =
t90% (Driver 2) =
PROBLEM 5: Drivers
The following circuit is supposed to represent a better driver structure.
a. Determine how the circuit operates by drawing the waveforms at nodes X , and Out dur- ing a high-to-low transition at the input. Assume that C (^) s << Cb.
b. Derive an approximate expression for the voltage at node X at the end of the transition.
c. Describe briefly why this leads to a better buffer.
In Figure: Driver
C Out s (^) C b
VDD
X
t
X
t
Out
PROBLEM 6: Logic
The figure below shows an alternative implementation of Complementary Pass-tran- sistor logic.
a. Determine the logic function of the gate.
b. Discuss why this logic family would be preferable over traditional NMOS-only CPL and full CMOS transmission gate pass-transistor logic.
Figure: Logic
DD
O =
O =
iii) with respect to performance
ii) with respect to noise margins
i) with respect to implementation complexity
