Memory unit - Engineering Systems and Design - Exam, Exams of Systems Engineering

Main points of this past exam are: Memory Unit, Input Interface, Output Interface, Processing Unit, Sequence, Implemented, Monostable Directional

Typology: Exams

2012/2013

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Cork Institute of Technology
Bachelor of Engineering in Mechanical Engineering – Award
(EMECH_7-Y3)
Autumn 2008
Engineering Systems and Design - ENGINEERING SYSTEMS
(Time: 3 Hours)
Answer Four Questions Examiner: Dr. M. J. O’Mahony
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Cork Institute of Technology

Bachelor of Engineering in Mechanical Engineering – Award

(EMECH_7-Y3)

Autumn 2008

Engineering Systems and Design - ENGINEERING S YSTEMS

(Time: 3 Hours)

Answer Four Questions Examiner: Dr. M. J. O’Mahony

  1. The structure of programmable logic controllers (PLCs) can be split into four basic components: Input interface. Output interface. Processing unit (CPU). Memory unit.

Describe the relationship between and the function of the above four basic components. (25 Marks)

  1. The following sequence is to be implemented using a PLC and monostable directional control valves. A+ B+C+B-C- B+C+B-C- B+C+B-C-A-

(i) How many groups are required are required if a cascade system is used? (5 Marks)

(ii) Draw a SiemensS7 ladder diagram for the above sequence. Use a counter to simplify the solution. Assume that all internal PLC relays have to be latched. (20 Marks)

Use the attached pneumatic circuit (FigQ2) as a aid to numbering the solenoids and limit switches.

The following nomenclature is to be used: A, B, C:Double acting pneumatic cylinders A+, etc:The extend stroke of cylinder A A+p: The pilot signal to cause the A+ stroke of cylinder A A-p: The pilot signal which initiates the return stroke of cylinder A A (^) d : The logic complement of A-p, used to reset single solenoid valves by disabling the latch function.

V,W: Internal PLC relays which can be set on or off V (^) p : Signal which sets relay V _ V (^) p : Signal which resets relay V V (^) d : The logical complement of Vp which disables relay V by disabling the latch.

Use the symbol table given in Table Q2.

Figure Q.

Name Address Comment

a0 I0.0 A retract limit switch a1 I0.1 A extend limit switch b0 I0.2 B retract limit switch b1 I0.3 B extend limit switch c0 I0.4 C retract limit switch c1 I0.5 C extend limit switch S1 I0.6 Main start switch a_sol Q0.0 A Solenoid b_sol Q0.1 B Solenoid c_sol Q0.12 C Solenoid COUNTER C60^ COUNTER W M1.0 MEMORY BIT W

Table Q