Memory Write Ability and Storage Permanence - Lecture Slides | ECE 332, Assignments of Microprocessors

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• ECE332, Week
• October 31,

Topics

Memory Write Ability and Storage Permanence

Common Memory Types

Composing Memory

DRAM

Write Ability

Ranges of write ability

High end

processor writes to memory simply and quickly

e.g. RAM

Middle range

processor writes to memory, but slower

e.g. FLASH, EEPROM

Lower range

special equipment, “programmer”, must be used to write to memory

e.g. EPROM, OTP ROM

Low end

bits stored only during fabrication

e.g., Mask-programmed ROM

In-system programmable memory

memoryCan be written to by a processor in the embedded system using the

Memories in high end and middle range of write ability

Storage Permanence

Range of storage permanence

High end

essentially never loses bits

e.g. mask-programmed ROM

Middle range

holds bits days, months, or years after memory’s power source turned off

e.g. NVRAM

Lower range

holds bits as long as power supplied to memory

e.g. SRAM

Low end

begins to lose bits almost immediately after written

e.g. DRAM

Nonvolatile memory

Holds bits after power is no longer supplied

High end and middle range of storage permanence

Example: 8x4 ROM

Horizontal lines = words

Vertical lines = data

Lines connected only at circles

address input is 010Decoder sets word 2’s line to 1 if

Data lines Q

3

and Q

1

are set to 1

connection with word 2’s linebecause there is a “programmed”

lines QWord 2 is not connected with data

2

and Q

0

Output is 1010

8

4 ROM

3
8

decoder

Q

0

Q

3

A

0

enable A

2

word 1word 0

A 1 Q 2 Q 1

programmable connection

wired-OR

data line word line

word 2

Internal view

Implementing Combinational Function

Any combinational circuit of

n

functions of same

k

variables can be done with 2

k

x

n

ROM

Truth table

Inputs (address)

Outputs

a

b

c

y

z

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

1

0

1

0

1

1

1

1

1

0

1

1

1 1 1 1 1 0 0

0

1

0

1

1

0

1

0

1

1

1

1

1

1 z

y

c

enable

a b

2 ROM

word 7 word 1word 0

OTP ROM: One-Time Programmable ROM

Connections “programmed” by user

user provides file of desired contents of ROM

file input to machine called ROM programmer

each programmable connection is a fuse

not existROM programmer blows fuses where connections should

Very low write ability

devicetypically written only once and requires ROM programmer

Very high storage permanence

more fuses blownbits don’t change unless reconnected to programmer and

Commonly used in final products

cheaper, harder to inadvertently modify

EPROM: Erasable Programmable ROM

transistorProgrammable component is a MOS

insulatorTransistor has “floating” gate surrounded by an

(a)

Negative charges form a channel between source

and drain storing a logic 1

(b)

Large positive voltage at gate causes negative

floating gate storing a logic 0charges to move out of channel and get trapped in

(c)

(Erase) Shining UV rays on surface of floating-gate

floating gate restoring the logic 1causes negative charges to return to channel from

(d)

An EPROM package showing quartz window

through which UV light can pass

Better write ability

of timescan be erased and reprogrammed thousands

Reduced storage permanence

susceptible to radiation and electric noiseprogram lasts about 10 years but is

developmentTypically used during design

(d) (b) (a)

source

drain

+15V

source

drain

0V

(c)

source

drain

floating gate

5-30 min

Flash Memory

Extension of EEPROM

Same floating gate principle

Same write ability and storage permanence

Fast erase

word at a timeLarge blocks of memory erased at once, rather than one

Blocks typically several thousand bytes large

Writes to single words may be slower

written backEntire block must be read, word updated, then entire block

items in nonvolatile memoryUsed with embedded systems storing large data

e.g., digital cameras, TV set-top boxes, cell phones

RAM: “Random-access” memory

Typically volatile memory

No power - no bits!

R

ead and written to easily by embedded

system during execution

Internal structure more complex than ROM

each storing 1 bita word consists of several memory cells,

ea

ch input and output data line connects to

each cell in its column

rd/wr connected to every cell

when rd/wr indicates readrd/wr indicates write or outputs stored bithas logic that stores input data bit whenwhen row is enabled by decoder, each cell

enable

k

n read and write

memory

A

0

…

r/w

…

Q

0

Q

n-

A

k-

external view

4
4 RAM 2
4

decoder

Q

0

Q

3

A

0

enable

A 1 Q 2 Q 1

Memory

cell

I 0

I 3

I 2

I 1

rd/wr

To every cell

internal view

RAM Variations

PSRAM: Pseudo-static RAM

DRAM with built-in memory refresh controller

Popular low-cost high-density alternative to SRAM

NVRAM: Nonvolatile RAM

Holds data after external power removed

Battery-backed RAM

SRAM with own permanently connected battery

writes as fast as reads

memoryno limit on number of writes unlike nonvolatile ROM-based

SRAM with EEPROM or flash

power turned offstores complete RAM contents on EEPROM or flash before

Composing memory

readily available memoriesMemory size needed often differs from size of

linesunneeded high-order address bits and higher dataWhen available memory is larger, simply ignore

several smaller memories into one larger memoryWhen available memory is smaller, compose

Connect side-by-side to increase width of words

Connect top to bottom to increase number of words

using a decodersmaller memory containing desired wordadded high-order address line selects

wordsCombine techniques to increase number and width of

…

2 m

3n ROM

2 m

n

ROM

A

0

…

enable

2 m

n

ROM

…

2 m

n

ROM

…

Q

3n-

Q

2n-

…

Q

0

…

A

m

Increase width

of words

2 m+

n ROM

m

n ROM

A

0

…

enable

…

m

n ROM

A

m-

A

m

1 (^)
(^2)

decoder

…

…

…

Q

n-

Q

…

Increase number of words

enable A

outputs

Increase number

and width of

words

DRAM Integration Problem

SRAM easily integrated on same chip as processor

DRAM more difficult

conventional logicDifferent chip making process between DRAM and

Goal of conventional logic (IC) designers:

delays and power consumptionminimize parasitic capacitance to reduce signal propagation

Goal of DRAM designers:

create capacitor cells to retain stored information

Integration processes beginning to appear

Memory Management Unit (MMU)

Duties of MMU

arbitrationHandles DRAM refresh, bus interface and

processorsTakes care of memory sharing among multiple

DRAMprocessor to physical memory addresses ofTranslates logic memory addresses from

Modern CPUs often come with MMU built-in