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Microprocessor Applications - Old Exam Questions 2004 | EEL 4744, Exams of Microprocessors

University of Florida (UF)Microprocessors
Prof. Karl S. Gugel

Material Type: Exam; Professor: Gugel; Class: MICROPROCESSOR APPLIC; Subject: ENGINEERING: ELECTRICAL; University: University of Florida; Term: Fall 2004;

Typology: Exams

Pre 2010

Uploaded on 09/17/2009

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EEL 4744C – Dr. Gugel Last Name_________________________ First Name_______________
Fall Semester 2004
Exam #2 UF Student ID#____________________________________
• Open book and open notes, 90-minute examination to be done in pencil.
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Calculators are permitted!
• All work and solutions are to be written on the exam where appropriate.
Point System
Page 2 21 points _________________
Page 3 20 points _________________
Page 4 16 points _________________
Page 5 16 points _________________
Page 6 9 points _________________
Page 7 18 points _________________
TOTAL _________________out of 100
Grade Review Information: (NOTE: deadline of request for grade review is the day the exam is returned.)
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Download Microprocessor Applications - Old Exam Questions 2004 | EEL 4744 and more Exams Microprocessors in PDF only on Docsity!

EEL 4744C – Dr. Gugel Last Name_________________________ First Name_______________

Fall Semester 2004

Exam #2 UF Student ID#____________________________________

• Open book and open notes, 90 - minute examination to be done in pencil.

• Calculators are permitted!

• All work and solutions are to be written on the exam where appropriate.

Point System

Page 2 21 points _________________

Page 3 20 points _________________

Page 4 16 points _________________

Page 5 16 points _________________

Page 6 9 points _________________

Page 7 18 points _________________

TOTAL _________________out of 100

Grade Review Information: ( NOTE: deadline of request for grade review is the day the exam is returned .)

__________________________________________________________________________________________

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Part A. Fill in da Blanc.

  1. What term is used to describe the subsystem in a modern CPU that can transfer data between the internal cache and external memory without using the ALU. (2 pt.)
  1. A designer of a stand-alone microprocessor system desires that parameters be saved when the system is powered off (i.e. cell phone numbers in a cell phone), name TWO different types of memory that can be used in this application. (2 pt.)
  1. A student is working on an application with their 6812 development board that uses interrupts on Timer Channel 3 (TC3), the Serial Communication Interface 0 (SCI0), /IRQ, and the Real Time Interrupt (RTI). By coincidence they all fire at exactly the same time, what is the order in which the ISRs will be executed on the CPU. (2 pt.) 1 st^ = ________________ 2 nd^ = __________________ 3 rd^ = __________________ 4 th^ = ___________________
  2. A student has connected a 16C550 UART to their board and would like to send out the number 5 repeatedly for test purposes. Draw the expected signal below at the UART’s TX pin assuming 1 start bit, 8 data bits, 1 stop bit and even parity at 4800 BAUD. Assuming that we will view this on a digital scope, also label the Y & X axis and show the bit width period value in micro-seconds. (8 pt.) | | |____________________________________________________________________________________________________ | | |
  3. In the above problem, what percent is overhead in this type of communication? What is the efficiency percent? (3 pt.)
  1. Two CPUs use flags to transfer data over a bus in the following manner:
  2. CPU#1 asserts an output signal, DataRequest, to tell CPU#2 to free up the bus and waits until an input, DataGranted, is true.
  3. CPU#2 releases the data bus and then sets DataGranted true.
  4. CPU#1 writes a value to the data bus and then sets DataRequest false.
  5. CPU#2 reads the value off of the bus and then sets DataGranted false. What type of communication is this? (2 pt.) __________________________________________________________________
  6. On the 6812 if we wanted to allow other interrupts to fire during the RTI ISR what would we have to do? (2 pt.)

Part D. Bus Driving & Fan Out A student would like to add several output ports to their board such that several hundred LEDs can be turned on and off. Given the following table of specifications, answer the questions below: 68HC12 Data Bus 74F374 74HC374 Units IOL Maximum 40 30 22 mA IOL Minimum 37 25 17 mA IOH Maximum - 36 - 29 - 22 mA IOH Minimum - 30 - 27 - 17 mA IIL Maximum - 160 - 300 - 180 uA IIL Minimum - 140 - 240 - 160 uA IIH Maximum 180 220 150 uA IIH Minimum 170 200 140 uA

  1. If the output ports are created from F chips only , how many ports can theoretically be added to the bus in the worst case? (4 pt.) Number of F output ports theoretically possible = _____________________________________________________________
  2. If the student has attached 50 F ports to the bus and has run out of F devices, how many “HC” ports can be added in the worst case? (4 pt.) Number of HC output ports theoretically possible when added to 50 F output ports already on the bus = ______________________ Part D. I/O Ports and Memory Decoding.
  3. The student above has decided to switch from the 68HC12 to a general purpose microprocessor that has address lines A15:0 , data D15:0 , R/-W and a simple data strobe – DS. Draw the decode circuit and port circuitry required to place a single word wide output port from $7800-$7BFF assuming that only F374s are used. (8 pt.)

Part D. I/O Ports and Memory Decoding Continued. Assume that you still have the general purpose microprocessor that contains address lines A15:0 , data D15:0 , R/-W and a simple data strobe – DS.

  1. Show the decode circuit and port circuitry to place a single word wide input port at $7800 to read switches assuming that there will be 256 images of the port in the memory map. You are only allowed to use F374s are should show a decode circuit, port circuit and how the switches are connected to the port circuitry. (8 pt.)
  2. Using the same general purpose processor ( A15:0 , D15:0 , R/-W and – DS ) and 4Kx8 SRAM draw the decode circuit and SRAM devices to place 8K words of memory (SRAM) starting at $3000. (8 pt.)
  1. If the write timing diagram changes such that R/-W signal goes high on a write cycle at exactly the same time as – DS going false, what must the CPLD propagation be less than or equal to for generation of – CE? (2 pt.)
  1. If the CPLD used for decoding the – CE signal has a propagation delay of 10 nsec, what must the access time of the memory be equal to or less than? (4 pt.)

Part F. 68HC12 Timing Mechanisms

  1. You are given a 68HC12 student development board that has a 8 MHz external crystal for the processor clock. What is the slowest rate at which the RTI interrupt will run in Hz? (2 pt.)
  1. Assuming that the RTI will be used at its slowest rate, how many interrupts will fire in 5 minutes? (2 pt.) _____________________
  2. Assume that the RTI has already been initialized, create an ISR to pulse Port T0 low/high/low every 5 minutes. You can assume that Port T0 has already been set as an output and that the pulse only has to be high for a duration equal to or greater than 10 nsec. RTI_ISR (8 pt.)