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Practice Exam 2 on Microprocessors Applications | EEL 4744, Exams of Microprocessors

University of Florida (UF)Microprocessors
Prof. Karl S. Gugel

Material Type: Exam; Professor: Gugel; Class: MICROPROCESSOR APPLIC; Subject: ENGINEERING: ELECTRICAL; University: University of Florida; Term: Spring 2005;

Typology: Exams

Pre 2010

Uploaded on 09/17/2009

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EEL 4744C – Dr. Gugel Last Name_________________________ First Name_______________
Spring Semester 2005
Exam #2 UF Student ID#____________________________________
• Open book and open notes, 90-minute examination to be done in pencil.
•
Calculators are permitted!
• All work and solutions are to be written on the exam where appropriate.
Point System
Page 2 20 points _________________
Page 3 24 points _________________
Page 4 14 points _________________
Page 5 12 points _________________
Page 6 15 points _________________
Page 7 15 points _________________
TOTAL _________________out of 100
Grade Review Information: (NOTE: deadline of request for grade review is the day the exam is returned.)
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Download Practice Exam 2 on Microprocessors Applications | EEL 4744 and more Exams Microprocessors in PDF only on Docsity!

EEL 4744C – Dr. Gugel Last Name_________________________ First Name_______________

Spring Semester 2005

Exam #2 UF Student ID#____________________________________

• Open book and open notes, 90 - minute examination to be done in pencil.

• Calculators are permitted!

• All work and solutions are to be written on the exam where appropriate.

Point System

Page 2 20 points _________________

Page 3 24 points _________________

Page 4 14 points _________________

Page 5 12 points _________________

Page 6 15 points _________________

Page 7 15 points _________________

TOTAL _________________out of 100

Grade Review Information: ( NOTE: deadline of request for grade review is the day the exam is returned .)

__________________________________________________________________________________________

__________________________________________________________________________________________

__________________________________________________________________________________________

__________________________________________________________________________________________

__________________________________________________________________________________________

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Part A. General Questions.

  1. Identify two non-maskable and two maskable interrupts on the 68HC12. (4 pt.) non-maskable interrupts => ______________________________________ and ________________________________________ maskable interrupts => ______________________________________ and ________________________________________
  2. Identify two types of volatile memory (2 pt.) _________________________________________ and ____________________________________________
  3. A student would like to use /IRQ on their 68HC12 board. If the interrupt handler, IRQ_ISR , is going to be placed in EPROM, write the code required to connect the /IRQ interrupt vector to the IRQ_ISR handler. (2 pt.)
  1. Describe how a watchdog timer interrupt functions. (2 pt.)
  1. Given the following device characteristics below. Answer the questions that follow. 74Fxx Family Devices 74HCxx Family Devices Max Min Max Min VOH N/A 3.7V N/A 4.5V IOH - 18mA - 16mA - 15mA - 12mA VOL 0.7V N/A 0.5V N/A IOL 25mA 22mA 20mA 18mA VIH N/A 2.2V N/A 2.0V IIH 400uA 350uA 300uA 280uA VIL 1.5V N/A 1.8V N/A IIL - 500uA - 450uA 350uA 300uA What is the worst case fan-out for 74Fxx devices driving 74HCxx devices? _________________________________________ (4 pt.) What are the worst case noise margins for the 74HCxx family? ___________________________________________________ (4 pt.) When current is flowing into the output of a TTL device, what do we call this effect? _________________________________ (2 pt.)

Part C. SRAM, Latches, Buffers and Memory Maps Assume that you have a uP that has a 16 bit Address bus and 8 bit data bus. The address bus is only available on the first half of the memory cycle and then it tri-states for the remaining portion of the cycle. A signal – ALE (Address Latch Enable) is available for latching the address where address is assumed to be valid only when – ALE goes low. The uP also has a R/-W signal and a +DS (data strobe) where data is written and read on the falling edge of +DS. Assume you only have the following devices: (100) 2 input NAND gates , (10) 74LS574 s, (10) 8Kx8 SRAMs , (10) 8Kx8 EPROM s

  1. Show the circuitry necessary to keep A15:0 constant throughout the memory cycle. Show all ICs required and connected signals. (6 pt.)
  2. Create both an input & output port at $F000 with 4K images. Draw the I/O port circuitry, connected signals and decode circuit, using NANDs only for decoding. (8 pt.)

A15:

D7:

A15:

- ALE

D7:

+DS

  1. Fill the Memory Map from 0-$FFF with EPROM and $2000-$5FFF with SRAM. Show all required ICs, connected signals and the decode circuit using NANDs only. Assume full address decoding. (12 pt.)
  1. Interrupt Handler Code (8 pt.):
  1. If we used the Output Compare Timer instead of Overflow to generate an interrupt timing interval equal to 1 msec , what would we have to add to the output compare register (i.e. TC0) each time in the interrupt to generate a new interrupt? Assume the same specifications listed in the beginning of Part D where TCNT was set to increment at its fastest rate possible. (3 pt.)
  2. If we use Input Capture as the mechanism to capture TCNT on the rising edge of the signal going to PT0 and on the falling edge of this signal, explain the steps required to compute the number of hours the signal was high after these two interrupts fire. Assume the same specifications listed in the beginning of Part D and that the Output Compare Timer in #4 is not being used. (4 pt.)