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This lecture was delivered by Sir Ravi Pratap at Bengal Engineering
Typology: Slides
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Memory
Outputunits
Inputunits
Bus
MicroprocessorControl
unitDatapathALUReg. ⎯^ Microprocessors are the brains of the systems ⎯^ Microprocessors access memories and other units through buses ⎯^ The operations of microprocessors are controlled by instructionsstored in memories
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2
PC IR Controlunit ALU
Memory Addr Reg
Address bus Control bus Data bus
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4
Http://history.acusd.edu/gen/recording/computer1.htmlhttp://www.cs.virginia.edu/brochure/museum.htmlhttp://www.columbia.edu/acis/history/650.html
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Http://history.acusd.edu/gen/recording/computer1.htmlhttp://www.computer50.org/kgill/transistor/trans.html
Manchester University Experimental Transistor Computer
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7
ALU Instructiondecoder
Reg. Programcounter
I/O^
Refreshlogic System bus Control logic ROM/RAM buffer
Timing^
Reset
http://www.intel.com
A good review article: The History of The Microprocessor, Bell Labs Technical Journal,
Autumn, 1997 Block diagram of Intel 4004
4004 chip layout
8
100001000 100 10 11974
1979 1982
1985
1989 1993
1997
1999 2000
(^80888080)
(^8038680286)
Pentium^80486
P IIP III
P 4
7 6 5 4 3 2 1 01974
1979 1982
1985
1989 1993
1997
1999 2000
8080 8088
(^8038680286)
Pentium 80486
P II^ P III
P 4
1,000,000100,00010,0001,000^100101 100,000,00010,000,
1974 1979
1982 1985 1989
1993 1997 1999
2000
(^80888080)
(^80386 )
Pentium 80486
P IIIP II P 4
10000100010010 1 0.1^1974
1979 1982
1985 1989
1993 1997 1999
2000
(^80888080)
(^8038680286)
Pentium 80486
P IIIP II P 4
Number of transistors
Minimum transistor sizes (μm)
Clock frequencies (MHz)
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14
20-bitaddress
8-bit data
controlsignalsTo 8088
controlsignalsfrom 8088
8088 signal classification
Memory locations
High byte of wordLow byte of word
Word: 5A2F
15
AH^
AL BH^
BL CH^
CL DH^
DLSPBPSIDI ALU Flag register
Execution Unit(EU)
EUcontrol
Σ CSDSSSES
ALU Data bus(16 bits)
Address bus (20 bits) Instruction Queue
Buscontrol
External bus IP
Data bus(16 bits)
Bus Interface Unit (BIU)
General purposeregister
Segmentregister
16
15
8 7
0
AccumulatorBaseCounterData
SP BP SI DI
Data Group Pointer andIndex Group
Stack PointerBase PointerSource IndexDestination Index
17
⎯^
⎯^
Interrupt enable flag DF:^
Direction flag TF:^
Trap flag
Carry flag PF:^
Parity flag AF:^
Auxiliary carry flag ZF:^
Zero flag SF:^
Sign flag OF:^
Overflow flag
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ALU Data bus(16 bits) AH^
AL BH^
BL CH^
CL DH^
DLSPBPSIDI
General purposeregister ALU Flag register
EUcontrol
instruction 1011000101001010
An arithmetic operation ¾ A logic operation ¾ Storing a datum into a register ¾ Moving a datum from a register ¾ Changing flag register
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Segment(64K)
16-bit register16-bit register20-bit memory address
Left shift 4 bits Intel 80x86 memory address generation
1M memory space
OffsetSegmentaddress
Offset
Addr Addr1 + 0FFFF
20
0 Code SegmentData SegmentStack SegmentExtra Segment
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