Quiz 1
Q1: contrast between 88 and 86 architecture
A: both processor are 16 bit
IO/M is changed (M is active low in 88, while IO is active low in 86)
Data bus 8 bit in 88 16 bit in 86
Prefetch queue is 1byte and 4 level deep in 88
while prefetch queue is 2 byte wide and 3 level deep
Q2: data types supported by 88 and ALU of 88
A: ALU supports 8 and 16 bit while 88 support 8,16,32 bit
Q3: Block diagram of internal architecture
A: in the book
Q4: identify address and data bus of 256K x 16 bit memory
A: address bus 18 bit and data bus 16 bit
Q5: Difference between Von-Neumann & Harvard architecture
A: in first same interface for code and data memories
While in Harvard separate interfaces for code and data memories
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Quiz 2
Q1: List the registers which can not be used in assemble mode
A: CS and IP
Q2: Generate the address of the mov al, [BP+BX+2000]
Wrong instruction (both base or index register can not be used in single instruction
Q3: what is wrong with mov AL,CX instruction
A: data mismatch
Q4:Does mov ax,bx
Mov bx,ax is equivalent to XCHG AX,BX
A: No
Q5) How Push [DI] works
A: Push instruction pushes word of data so SP-1 will contain HB and SP-2 will contain
LB
Q6) Write the name of the categories with one example for which 88 instruction are
classified
A: i) data movement/transfer instructions
ii) Arithmetic instructions
iii) bit manipulation instruction
iv) string instruction (movs,stos,lods,scas,cmps)
v) Program memory instruction (jmp, call, ret, reti)
vi) Processor control instruction (nop, cli,sti, cld, std, hlt, wait)
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Quiz 3
Q1: Write code to transfer 2 bytes from ES using BX register
A: segment override prefix will be used
mov ax, 2000
mov es,ax
mov ax,ES: [BX]
inc BX
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