Microprocessor Programming - 8086hardware, Study notes of Microprocessors

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8086/8088 Hardware

Specifications

Basic Hardware and Timing Notations for

MPU

• (^) T-State:
  • (^) It is defined as time taken by single clock pulse or

subdivision of operation performed in one clock.

• (^) Machine Cycle:
  • (^) It is defined as time required by processor to access either

memory or I/O for reading or writing data or code. Machine

cycle may be composed 3 to 6 T states.

• (^) Instruction Cycle:
  • (^) It is defined as time required by processor to completely

fetch and execute an instruction. An instruction cycle may

composed of one to six machine cycles

Minimum and Maximum Mode

• Minimum Mode

– When only a single microprocessor controls all the

buses it is called Minimum Mode

• Maximum Mode

– When more than one microprocessor share same

set of buses it is called Maximum Mode.

• PIN No. 33 of 8086 (MN, /MX), determines

Minimum Mode or Maximum mode for MPU

MN , MX

Intel 8086/8088 Microprocessors

• Intel 8086 and 8088 Microprocessors are the basis of all

IBM-PC compatible computers

(8086 introduced in 1978, first IBM-PC released in 1981)

• All Intel, AMD and other advanced microprocessors are

based on and are compatible with the original 8086/

• At Power Up and Reset time, Pentiums, Athlons etc all look

like 8086 processors

• Intel 8086 is a 16b microprocessor:

• 16b data registers, 16b ALU

• Width of external data bus:

• (^) 8086: 16b
• (^) 8088: 8b

• Width of external address bus: 16b+4b= 20b

Intel 8086/8088 Microprocessors

• It uses fetch with decoding techniques to optimise

the CPU performance when it’s executing programs

• Segment: Offset memory model helps in

performing multi tasking.

• Fetching from EXTERNAL MEMORY is SLOW

– The 8086/8 used an instruction queue to speed up

performance

– While the processor is decoding and executing an

instruction, its bus interface can be reading new

instructions, since at that time the bus is not actually in

use

PIN CONFIGURATION 8086/ 11/27/

Minimum Mode Pins

De-multiplexing the Buses of the 8086

• (^) Two 74LS373 transparent latches are used to de- multiplex the address/data bus connections AD15-AD0 and the multiplexed address/status connections A19/S6-A16/S3.
• (^) These transparent latches, which are like wires whenever the address latch enable pin (ALE) becomes a logic 1, pass the inputs to the outputs. After a short time, ALE returns to its logic 0 condition, which causes the latches to remember the inputs at the time of the change to a logic 0.
• (^) In this case, A15-A0 are stored in the bottom latch and A19-A16 are stored in the top latch.

Maximum Mode Pins

The status bits indicate the function of the

current bus cycle. These signals are normally

decoded by the 8288 bus controller.

S2 S1 S0 Function

0 0 0 Interrupt acknowledge

0 0 1 I/O read

0 1 0 I/O write

0 1 1 Halt

1 0 0 Opcode fetch

1 0 1 Memory read

1 1 0 Memory write

1 1 1 Passive

74 LS 245

x 2

8284 A

Clock Generator RDY Vcc 8086 CPU

CLK

READY

RESET

MN/MX#

S 0

S 1

S 2

8288 Bus Controller

MRDC#

MWTC#

AMWC#

IORC#

IOWC#

AIOWC#

INTA#

CLK

74 LS 373

x 3 ADDR/DATA

LE

OE#

ALE

DEN

DT/R#

BHE

AD 15 :AD 0

A 19 :A 16

74 LS 245

x 2

EN#

DIR

D 15 :D 0 A 19 :A 0 , BHE# ADDR/Data

INTR

i 8086 Circuit - Maximum Mode

• PIN CONFIGURATION
• The Fully Buffered