Microprocessor Programming - Essential Devices with 8086, Study notes of Microprocessors

Download Microprocessor Programming - Essential Devices with 8086 and more Study notes Microprocessors in PDF only on Docsity!

• Essential Devices with

• • • (^) Clock Generator (8284A)Bus Controller (8288)
• Octal Transparent Latch With 3-state Outputs^ (74HC373)Buffered Unidirectional Octal Bus (74HC
• (^) Buffered Bidirectional Octal Bus Transmitter / Receiver (74HC245)

• (^) X1 and X2: Crystal Oscillator pins. Connect a crystal of theClock Generator (8284A): Signals
• correct frequency between these two terminals to^ generate the clock signal.EFI clocking source to the 8284A oscillator.: External frequency input. Signal can be used as the instead of the crystal
• • (^) F/#C oscillator (0) as the clocking source for the 8284ACLK the CLK input on the 8086/8088. At 1/3 rd of the crystal or EFI input frequency with 1:3 duty cycle: f output: The clock signal produced for connecting to input: Selects external EFI input (1) or the crystal
• (^) OSC Connect to EFIs on systems (synchronized clocks) fosc = f: Oscillator output. Same frequency as crystal or EFI.xtal= fEFI other 8284As in multiprocessorclock^ = fxtal/3 = fEFI/
• • (^) PCLK crystal or EFI input frequency (1/2 clock freq) with 1:2 duty cycle. Use to drive peripheral equipment in the system fCSYNC output: peripheral clock signal at 1/6 th of the input: Clock synchronization input. Should be usedpclk = fxtal/6 = fEFI/ if EFI is used, otherwise must be grounded.

Clocks & Clock Synchronization Signals

Crystal

XTAL or EFI  3^ OSC:^ EFI To other  2^ m CLK toPs^ PCLK to Per m P

Clock Generator (8284A): Signals

• (^) #AEN1 with output. The READY output is connected to the READY input on the 8086/8088 RDY1 and and #AEN2 RDY2 address enable inputs: Used inputs to generate the mP to control READY
• memory wait states.#ASYNC Selects 1 or 2 stages of synchronization for the RDY1 and RDY2 inputs. input: for READY output synchronization.

READY Signals

• (^) #RES an RC circuit to provide automatic reset at power on.^ RESET Signals Reset input: Active low. Usually connected to
• (^) RESET 8086/8088 RESET input. output: Synchronized to Clk. Connect to the

frequency, f f/

RC circuit for automatic Reset on power up

Grounded when Xtal Osc is used^ PCLK^ f/6 2.5 MHz

Manual Reset push button Switch

Typical Application of the 8284A for clock and Reset signal generation

RC time constant large enough for 50 at worst trigger conditions (1.05 V Threshold) ms min Reset pulse

RESET (^50) Minimum ms Effective Digital #RES Input

R

C

OSC (^) f 15 MHz Synced To CLK

(Not Transceivers) Use to determine Fanout

A-B: Open circuit, No connection