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slides of microprocessor book of chapter 8 and 9 and 10
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(^) Delivering different amounts of data (^) At different speeds (^) In different formats
(^) Interface to CPU and Memory (^) Interface to one or more peripherals
Address Lines Data Lines Control Lines I/O Module System Bus Links to Peripheral Devices
(^) Screen, Printer, Keyboard
(^) Monitoring and control (^) Magnetic disks and Tape drives
(^) Modem (^) Network Interface Card (NIC)
(^) Control and timing (^) To coordinate the flow of traffic between internal resources and external devices (^) Processor communication (^) Communication between processor and I/O module (^) Device communication (^) Communication between device and I/O module (^) Data buffering (^) Necessary because of different data rates of processor and peripheral (^) Error detection (^) Unintentional changes to the bit pattern are detected
(^) Active (^) Either busy or ready (^) Inactive (no I/o operation) (^) Transition b/w these two states can be done by user application program. (^) R-t0-B transition is either due to user task or an event. (^) B-to R when event or task is completed. (^) Ready to inactive: by user program or due to expiration of predefined inactivity time interval.
(^) H.W = data producer (^) S.W= data consumer(receive and process data) (^) General process (^) H.W has produced and software read it and allow the HW to start new production.
(^) S.W = data producer (^) H.W= data consumer(receive and process data) (^) General process (^) If SW is faster it need to wait. In the absence of sync SW might wait longer than needed. Extra delay will occur. (^) If HW is faster it need to wait for software.
(^) Continuous poling or busy wait (^) Periodic polling
(^) I/O synchronization using interrupt (^) Direct Memory Access
(^) In an I/O operation there is a delay in HW responding to SW. (^) If this delay is highly predictable (^) Software can initiate a new request after fixed delay. This is what is done in blind cycle sync. (^) Choice of fixed time interval (^) Max possible time that is require by the HW to complete the operation. (^) (Disadvantage)If mean time for the device HW to complete the operation is significantly smaller than maximum time, results in unnecessary delay and waste processor time. (^) HW & SW operations performed sequentially so waste of resources (^) (Advantage) Implementation simplicity