ECE 331 Spring 2009 Homework 10 Solution: Memory Systems and Microcontroller Timers - Prof, Assignments of Electrical and Electronics Engineering

Solutions to homework 10 of ece 331 spring 2009 course. It covers calculations related to memory systems with 18 address lines and 16 data lines, and a microcontroller timer unit with a 16-bit counter operating at 1mhz. The document also includes diagrams of memory interfaces using hcs12 mcu and external sram chips.

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Pre 2010

Uploaded on 07/28/2009

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ECE 331 Spring 2009 Homework 10 -Solution
1. A memory system contains 18 address lines and 16 data lines. Specify:
a) number of addressable memory locations = 2m = 218 = 262,144 = 256K
b) memory width = # data lines = 16 bits
c) memory length = # of memory bytes = 218 = 262,144 = 256K
d) memory size in bytes = 218 = 262,144 = 256K
e) memory size in bits = # bytes * bytes/bit = 262,144 * 16 = 4,194,304 =
4Mbits
2. Consider a microcontroller timer unit with a 16-bit counter operating with a 1MHz clock:
a) What is the maximum count value (in decimal) of the counter?
216 = 65,536 = 64K
b) How long will it take for the counter to overflow?
216 = 65,536 = 64K
c) If the counter is used to time a 10 second event, how many times will the counter overflow
and what is the value (in hex) in the counter after 10 seconds? Assume the counter starts
at $0000.
1MHz 1 µ sec/count. 65,536 counts will take 65.536msec.
In 10 sec, the counter will overflow 10/(65.536m) = 152.59 152 times
The time taken for 152 overflow cycles is 152(65.536msec) = 9.661472 sec
(notice that here we MUST keep track of all the digits after the decimal)
The time remaining to count in the 153rd cycle is 10 - 9.661472 = 38.528msec
The count during the 153rd cycle would be 38.528m/1µ = 38,528 = $9680.
d) Repeat part c) if the counter is initially at $F0F0.
By inspection, this would cause the counter to overflow one additional time.
The counter value on the 154th cycle would be:
$F0F0 + $9680 = $18770, where the first digit represents the additional
overflow. Thus, the counter would hold $8870.
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ECE 331 Spring 2009 Homework 10 -Solution

1. A memory system contains 18 address lines and 16 data lines. Specify:

a) number of addressable memory locations = 2

m

18

= 262,144 = 256K

b) memory width = # data lines = 16 bits

c) memory length = # of memory bytes = 2

18

= 262,144 = 256K

d) memory size in bytes = 2

18

= 262,144 = 256K

e) memory size in bits = # bytes * bytes/bit = 262,144 * 16 = 4,194,304 =

4Mbits

2. Consider a microcontroller timer unit with a 16-bit counter operating with a 1MHz clock:

a) What is the maximum count value (in decimal) of the counter?

16

= 65,536 = 64 K

b) How long will it take for the counter to overflow?

16

= 65,536 = 64 K

c) If the counter is used to time a 10 second event, how many times will the counter overflow

and what is the value (in hex) in the counter after 10 seconds? Assume the counter starts

at $0000.

1MHz  1 μ sec/count. 65,536 counts will take 65.536msec.

In 10 sec, the counter will overflow 10/(65.536m) = 152.59  152 times

The time taken for 152 overflow cycles is 152(65.536msec) = 9.661472 sec

(notice that here we MUST keep track of all the digits after the decimal)

The time remaining to count in the 153

rd

cycle is 10 - 9.661472 = 38.528msec

The count during the 153

rd

cycle would be 38.528m/1μ = 38,528 = $.

d) Repeat part c) if the counter is initially at $F0F0.

By inspection, this would cause the counter to overflow one additional time.

The counter value on the 154

th

cycle would be:

$F0F0 + $9680 = $18770, where the first digit represents the additional

overflow. Thus, the counter would hold $.

3. Following examples from lecture, construct and diagram a memory interface using the

HCS12 MCU and external 1k-byte x 8-bit RAM chips (like the figure below). Show how an

external 4k X 16 RAM could be generated. Show all the necessary address, data, and control

signals.

The color-coded schematic below shows one method to realize this memory

interface using an active-low decoder to generate the chip enable for each 16-

bit block of memory. Alternatively, logic gates could be used to decode the

upper 2 bits of the 12-bit memory address.

D(7:0)

R/W CE

1kX SRAM

A (9:0)

D(7:0)

R/W CE

1kX SRAM

A (9:0)

D(7:0)

R/W CE

1kX SRAM

A (9:0)

D(7:0)

R/W CE

1kX SRAM

A (9:0)

D(7:0)

R/W CE

1kX SRAM

A (9:0)

D(7:0)

R/W CE

1kX SRAM

A (9:0)

D(7:0)

R/W CE

1kX SRAM

A (9:0)

D(7:0)

R/W CE

1kX SRAM

A (9:0)

Decoder

9:

11:0 9:

15:

10 11

9:

9:

9:

9:

9:

9:

9:

7:

7:

7:

7:

13:

13:

13:

13:

16-bit block 0 $000 - $3FF

$400 - $7FF

$800 - $BFF

$C00 - $FFF

16-bit block 1

16-bit block 2

16-bit block 3

MCU

R/W’

Data

Address