Download Microprocessors - Midterm Exam Questions | ECE 511 and more Exams Microprocessors in PDF only on Docsity!
George Mason University
ECE 511 Microprocessors
Midterm Exam – 18 October 2007
First Name: _____________ Last Name: ________________ GMU ID: _____________
1. (6 marks) Topic: General microprocessor concepts a. (3 marks) List and briefly describe the five classic components of a computer. Where does the Microprocessor fit in overall computer architecture?
Lecture Slides1A page 20
b. (3 marks) List and describe various (a) CPU instruction execution stages and (b) CPU elements.
Lecture Slides1A pages 28-
2. (6 marks) Topic: ISA a. (2 marks) Define ISA and describe the role of ISA in overall computer architecture.
Lecture Slides1A pages 15 and 22
b. (2 marks) What makes a machine big-endian or little-endian? Give an example.
Lecture Slides2 page 7
c. (2 marks) What are the differences between Base/Displacement and Indexed addressing modes?
Lecture Slides2 pages 44-
4. (6 marks) Topic: Computer Performance Evaluation and Metrics a. (2 marks) What is the formula/equation for the CPU time? Define each term in the equation.
Lecture Slides4 page 14
b. (4 marks) A machine, runs at a clock rate of 500 MHz has the following instruction classes: Instruction Class CPI Load/Store 3 Arithmetic/Logic 1 Branch 2
For a given program, two compilers produced the following instruction counts: Instruction count (in millions) Load/Store Arithmetic/Logic Branch GNU Compiler^5 1 Microsoft Compiler 10 1 2
Which compiler generated program runs better w.r.t (a) MIPS (b) CPU time?
Lecture Slides4 pages 30-
5. (6 Marks) Topic: Pipelining and Amdahl’s Law a. (1 mark) 10% of a program code executes 90% of the time, which is further enhanced by 20%. What is the overall speedup of the program?
Lecture Slides4 page 33
b. (1 mark) Identify all the possible hazards in the following instruction sequence.
lw r2, 0(r4) 1) Structural Hazard because of load add r1, r2, r3 2) Data Hazards (RAW, WAR, WAW) sub r2, r1, r add r2, r2, r1 Lecture Slides5 pages 25- sw r2, 0(r4)
c. (4 marks) Fill the pipelining diagram assuming single-port memory with five stage pipeline using forwarding as discussed in the class.
lw r2, 0(r4) (^) IF DR EX ME WR
add r1, r2, r3 (^) IF DR EX ME WR
sub r2, r1, r3 (^) IF DR EX ME WR
add r2, r2, r1 (^) IF DR EX ME WR
sw r2, 0(r4) (^) IF DR EX ME WR
Time (clock cycles)
Inst order
