Download PIO 8255 microprocessors and more Study notes Microprocessors in PDF only on Docsity!
M Krishna kumar
MAM/M3/LU9e/V1/
PIO 8255 (cont..)
•^
The parallel input-output port chip 8255 is also called asprogrammable
peripheral input-output port.
The Intel’s
8255 is designed for use with Intel’s 8-bit, 16-bit andhigher capability microprocessors. It has 24 input/outputlines which may be individually programmed in twogroups of twelve lines each, or three groups of eight lines.The two groups of I/O pins are named as Group A andGroup B. Each of these two groups contains a subgroup ofeight I/O lines called as 8-bit port and another subgroup offour lines or a 4-bit port. Thus Group A contains an 8-bitport A along with a 4-bit port. C upper.
M Krishna kumar
MAM/M3/LU9e/V1/
•^
The port A lines are identified by symbols PA
-PA 0
7
while
the port C lines are identified as PC
-PC 4
. Similarly, Group 7
B contains an 8-bit port B, containing lines PB
-PB 0
7
and a
4-bit port C with lower bits PC
- PC 0
. The port C upper 3
and port C lower can be used in combination as an 8-bitport C.
-^
Both the port C are assigned the same address. Thus onemay have either three 8-bit I/O ports or two 8-bit and two4-bit ports from 8255. All of these ports can functionindependently either as input or as output ports. This canbe achieved by programming the bits of an internal registerof 8255 called as control word register ( CWR ).
PIO 8255 (cont..)
M Krishna kumar
MAM/M3/LU9e/V1/
•^
This buffer receives or transmits data upon the executionof input or output instructions by the microprocessor. Thecontrol words or status information is also transferredthrough the buffer.
-^
The signal description of 8255 are briefly presented asfollows :
-^
PA
-PA 7
: These are eight port A lines that acts as either 0
latched output or buffered input lines depending upon thecontrol word loaded into the control word register.
-^
PC
-PC 7
4
: Upper nibble of port C lines. They may act as
either output latches or input buffers lines.
PIO 8255 (cont..)
M Krishna kumar
MAM/M3/LU9e/V1/
•^
This port also can be used for generation of handshakelines in mode 1 or mode 2.
-^
PC
-PC 3
0
: These are the lower port C lines, other details
are the same as PC
-PC 7
4
lines.
•^
PB
-PB 0
7
: These are the eight port B lines which are used
as latched output lines or buffered input lines in the sameway as port A.
-^
RD
: This is the input line driven by the microprocessor and should be low to indicate read operation to 8255.
-^
WR
: This is an input line driven by the microprocessor. A
low on this line indicates write operation.
PIO 8255 (cont..)
M Krishna kumar
MAM/M3/LU9e/V1/
Input (Read) cycle
RD
WR
CS
A^1
A^0
Port A to Data busPort B to Data busPort C to Data busCWR to Data bus
0 1 0
1
0
0
0 0 0 0
1
1 1
1 1 1
0
0 0 0
Output (Write) cycle
RD
WR
CS
A^1
A^0
Data bus to Port AData bus to Port BData bus to Port CData bus to CWR
0 1 0
0
0
0 0 0 0
1
0 1 1
0 0 0
1 1 1 1
Function
RD
WR
CS
A^1
A^0
Data bus tristatedData bus tristated
X X
X
1
X 1
X
0
X 1
Control Word Register
M Krishna kumar
MAM/M3/LU9e/V1/
•^
D
-D 0
: These are the data bus lines those carry data or 7
control word to/from the microprocessor.
-^
RESET
: A logic high on this line clears the control word
register of 8255. All ports are set as input ports by defaultafter reset.
PIO 8255.
M Krishna kumar
MAM/M3/LU9e/V1/
•^
Read/Write control logic
: This unit accepts control
signals ( RD, WR ) and also inputs from address bus andissues commands to individual group of control blocks( Group A, Group B).
-^
It has the following pins.
a)
CS
- Chipselect : A low on this PIN enables the communication between CPU and 8255.
b)
RD
(Read) – A low on this pin enables the CPU to read the data in the ports or the status word through data busbuffer.
Block Diagram of 8255 (Architecture)
( cont..)
M Krishna kumar
MAM/M3/LU9e/V1/
c)
WR
( Write ) : A low on this pin, the CPU can write
data on to the ports or on to the control register throughthe data bus buffer.
d)
RESET
: A high on this pin clears the control register
and all ports are set to the input mode
e)
A
0
and
A
1
( Address pins ): These pins in conjunction
with RD and WR pins control the selection of one of the3 ports.
-^
Group A and Group B controls
: These block receive
control from the CPU and issues commands to theirrespective ports.
Block Diagram of 8255 (Architecture)
( cont..)
M Krishna kumar
MAM/M3/LU9e/V1/
c)
Port C
: This has an 8 bit latched input buffer and 8 bit
Block Diagram of 8255 (Architecture).out put latched/buffer. This port can be divided into two 4bit ports and can be used as control signals for port A andport B. it can be programmed in mode 0.
M Krishna kumar
MAM/M3/LU9e/V1/
Modes of Operation of 8255 (cont..)
•^
These are two basic modes of operation of 8255. I/O modeand Bit Set-Reset mode (BSR).
-^
In I/O mode, the 8255 ports work as programmable I/Oports, while in BSR mode only port C (PC
-PC 0
) can be 7
used to set or reset its individual port bits.
-^
Under the I/O mode of operation, further there are threemodes of operation of 8255, so as to support differenttypes of applications, mode 0, mode 1 and mode 2.
M Krishna kumar
MAM/M3/LU9e/V1/
D^3
D^2
D^1
Selected bits of port C
0 1
D^0
0
0
0
0
0
0
1
1
0
1
1
1 1
0
0
0
1
1
1
0
1
1
D^1 D^2 D^3 D^4 D^5 D^6 D^7
BSR Mode : CWR Format
M Krishna kumar
MAM/M3/LU9e/V1/
17
8 2 5 5
8 2 5 5
PA PCUPCLPB
PA PCUPCLPB
PA6 – PA7PC4 – PC7PC0-PC3PB0 – PB
All Output
Port A and Port C acting asO/P. Port B acting as I/P
PA PC PB
Mode 0
M Krishna kumar
MAM/M3/LU9e/V1/
•^
The control word register has two formats. The first formatis valid for I/O modes of operation, i.e. modes 0, mode 1and mode 2 while the second format is valid for bitset/reset (BSR) mode of operation. These formats areshown in following fig.
D^6
D^7
D^0
D^1
D^2
D^3
D^4
D^5
1
X^
X^
X
0-for BSR mode
Bit select flags
0- Reset1- Set
I/O Mode Control Word Register Format
and
BSR Mode Control Word Register Format
D^3
, D
, D 2
are from 000 to 111 for bits PC 1
TO PC 0
7
Modes of Operation of 8255 (cont..)
M Krishna kumar
MAM/M3/LU9e/V1/ (^1234567891011121314151617181920)
40 39 38 37 36353433 323130 2928 27 26 25242322 21
PB
3 PB
4 PB
5 PB
6 PB
7 PAWRResetD^0 D^1 D^2 D^3 D^4 D^5 D^6 D^7 Vcc
7 PA
6 PA
5 PA
4
PB
2 PB
1 PB
0 PC
3 PC
2 PC
1 PC
0 PC
4 PC
5 PC
6 PC
7 PARDCSGNDA^1 A^0
0 PA
1 PA
2 PA
3
8255A
8255A Pin Configuration
