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Unit 3 – Microprogrammed Control
Hardwired Control Unit:
When the control signals are generated by hardware using conventional logic design techniques, the control unit is said to be hardwired.
Micro programmed control unit:
A control unit whose binary control variables are stored in memory is called a micro programmed control unit.
Dynamic microprogramming:
A more advanced development known as dynamic microprogramming permits a microprogram to be loaded initially from an auxiliary memory such as a magnetic disk. Control units that use dynamic microprogramming employ a writable control memory. This type of memory can be used for writing.
Control Memory: Control Memory is the storage in the microprogrammed control unit to store the microprogram.
Writeable Control Memory:
Control Storage whose contents can be modified, allow the change in microprogram and Instruction set can be changed or modified is referred as Writeable Control Memory.
Control Word:
The control variables at any given time can be represented by a control word string of 1 's and 0's called a control word.
Microoperation, Microinstruction, Micro program, Microcode.
Microoperations: In computer central processing units, micro-operations (also known as a micro-ops or μops) are detailed low-level instructions used in some designs to implement complex machine instructions (sometimes termed macro-instructions in this context).
Micro instruction:
A symbolic microprogram can be translated into its binary equivalent by means of an assembler. Each line of the assembly language microprogram defines a symbolic microinstruction. Each symbolic microinstruction is divided into five fields: label, microoperations, CD, BR, and AD.
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Unit 3 – Microprogrammed Control
Micro program: A sequence of microinstructions constitutes a microprogram. Since alterations of the microprogram are not needed once the control unit is in operation, the control memory can be a read-only memory (ROM). ROM words are made permanent during the hardware production of the unit. The use of a micro program involves placing all control variables in words of ROM for use by the control unit through successive read operations. The content of the word in ROM at a given address specifies a microinstruction.
Microcode:
Microinstructions can be saved by employing subroutines that use common sections of microcode. For example, the sequence of micro operations needed to generate the effective address of the operand for an instruction is common to all memory reference instructions. This sequence could be a subroutine that is called from within many other routines to execute the effective address computation.
Organization of micro programmed control unit
The general configuration of a micro-programmed control unit is demonstrated in the block diagram of Figure 4.1. The control memory is assumed to be a ROM, within which all control information is permanently stored.
figure 4.1: Micro-programmed control organization The control memory address register specifies the address of the microinstruction, and the control data register holds the microinstruction read from memory. The microinstruction contains a control word that specifies one or more microoperations for the data processor. Once these operations are executed, the control must determine the next address. The location of the next microinstruction may be the one next in sequence, or it may be located somewhere else in the control memory.
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Microprogrammed Control
Step-2:
The control memory next must go through the routine that determines the effective address of the operand. A machine instruction may have bits that specify various addressing modes, such as indirect address and index registers. The effective address computation routine in control memory can be reached through a branch microinstruction, which is conditioned on the status of the mode bits of the instruction. When the effective address computation routine is completed, the address of the operand is available in the memory address register.
Step-3:
The next step is to generate the microoperations that execute the instruction fetched from memory. The microoperation steps to be generated in processor registers depend on the operation code part of the instruction. Each instruction has its own micro-program routine stored in a given location of control memory. The transformation from the instruction code bits to an address in control memory where the routine is located is referred to as a mapping process. A mapping procedure is a rule that transforms the instruction code into a control memory address. Step-4:
Once the required routine is reached, the microinstructions that execute the instruction may be sequenced by incrementing the control address register. Micro-programs that employ subroutines will require an external register for storing the return address. Return addresses cannot be stored in ROM because the unit has no writing capability. When the execution of the instruction is completed, control must return to the fetch routine. This is accomplished by executing an unconditional branch microinstruction to the first address of the fetch routine.
In summary, the address sequencing capabilities required in a control memory are:
- Incrementing of the control address register.
- Unconditional branch or conditional branch, depending on status bit conditions.
- A mapping process from the bits of the instruction to an address for control memory.
- A facility for subroutine call and return.
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Microprogrammed Control
selection of address for control memory
Figure 4.2: Selection of address for control memory
Above figure 4.2 shows a block diagram of a control memory and the associated hardware needed for selecting the next microinstruction address. The microinstruction in control memory contains a set of bits to initiate microoperations in computer registers and other bits to specify the method by which the next address is obtained. The diagram shows four different paths from which the control address register (CAR) receives the address. The incrementer increments the content of the control address register by one, to select the next microinstruction in sequence. Branching is achieved by specifying the branch address in one of the fields of the microinstruction. Conditional branching is obtained by using part of the microinstruction to select a specific status bit in order to determine its condition. An external address is transferred into control memory via a mapping logic circuit. The return address for a subroutine is stored in a special register whose value is then used when the micro-program wishes to return from the subroutine.
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Microprogrammed Control
In this way the microprogram routine that executes the instruction can be placed in any desired location in control memory. The mapping concept provides flexibility for adding instructions for control memory as the need arises.
Computer Hardware Configuration
Figure 4.4: Computer hardware configuration The block diagram of the computer is shown in Figure 4.4. It consists of
- Two memory units: Main memory -> for storing instructions and data, and Control memory -> for storing the microprogram.
- Six Registers: Processor unit register: AC(accumulator),PC(Program Counter), AR(Address Register), DR(Data Register) Control unit register: CAR (Control Address Register), SBR(Subroutine Register)
- Multiplexers: The transfer of information among the registers in the processor is done through multiplexers rather than a common bus.
- ALU: The arithmetic, logic, and shift unit performs microoperations with data from AC and DR and places the result in AC.
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Unit 4 – Microprogrammed Control
DR can receive information from AC, PC, or memory. AR can receive information from PC or DR. PC can receive information only from AR. Input data written to memory come from DR, and data read from memory can go only to DR.
Microinstruction Format
The microinstruction format for the control memory is shown in figure 4.5. The 20 bits of the microinstruction are divided into four functional parts as follows:
- The three fields F1, F2, and F3 specify microoperations for the computer. The microoperations are subdivided into three fields of three bits each. The three bits in each field are encoded to specify seven distinct microoperations. This gives a total of 21 microoperations.
- The CD field selects status bit conditions.
- The BR field specifies the type of branch to be used.
- The AD field contains a branch address. The address field is seven bits wide, since the control memory has 128 = 2^7 words.
Figure 4.5: Microinstruction Format As an example, a microinstruction can specify two simultaneous microoperations from F2 and F3 and none from F1. DR M[AR] with F2 = 100 PC PC + 1 with F3 = 101 The nine bits of the microoperation fields will then be 000 100 101. The CD (condition) field consists of two bits which are encoded to specify four status bit conditions as listed in Table 4.1.
Table 4.1: Condition Field
The BR (branch) field consists of two bits. It is used, in conjunction with the address field AD, to choose the address of the next microinstruction shown in Table 4.2.
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Microprogrammed Control
Micro programmed sequencer for a control memory Microprogram sequencer:
The basic components of a microprogrammed control unit are the control memory and the circuits that select the next address. The address selection part is called a microprogram sequencer. A microprogram sequencer can be constructed with digital functions to suit a particular application. To guarantee a wide range of acceptability, an integrated circuit sequencer must provide an internal organization that can be adapted to a wide range of applications. The purpose of a microprogram sequencer is to present an address to the control memory so that a microinstruction may be read and executed. Commercial sequencers include within the unit an internal register stack used for temporary storage of addresses during microprogram looping and subroutine calls. Some sequencers provide an output register which can function as the address register for the control memory. The block diagram of the microprogram sequencer is shown in figure 4.6. There are two multiplexers in the circuit. The first multiplexer selects an address from one of four sources and routes it into a control address register CAR. The second multiplexer tests the value of a selected status bit and the result of the test is applied to an input logic circuit. The output from CAR provides the address for the control memory. The content of CAR is incremented and applied to one of the multiplexer inputs and to the subroutine registers SBR. The other three inputs to multiplexer 1 come from the address field of the present microinstruction, from the output of SBR, and from an external source that maps the instruction. Although the figure 4.6 shows a single subroutine register, a typical sequencer will have a register stack about four to eight levels deep. In this way, a number of subroutines can be active at the same time. The CD (condition) field of the microinstruction selects one of the status bits in the second multiplexer. If the bit selected is equal to 1, the T (test) variable is equal to 1; otherwise, it is equal to
The T value together with the two bits from the BR (branch) field goes to an input logic circuit. The input logic in a particular sequencer will determine the type of operations that are available in the unit.
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Microprogrammed Control
l 0 Input 3 2 1 0 Load
l 1 Logic
S
1
MU
X 1 SBR
T
S
0
1 Test^ Increment MUX 2
L Select
Clock CAR
Microo ps
Control Memory
CD BR
AD
Figure 4.6: Microprogram Sequencer for a control memory
Input Logic : Truth Table
BR Input MUX 1 Load SBR I1 I0 T S1 S0 L 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 0 1 1 0 1 1 1 0 1 0 X 1 0 0 1 1 1 1 X 1 1 0
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· A common bus system is employed to contact registers that are included in the CPU in a large number. Communications between registers is not only for direct data transfer but also for performing various micro-operations. A bus organization for such CPU register shown in Figure 3.2, is connected to two multiplexers (MUX) to form two buses A and B. The selected lines in each multiplexers select one register of the input data for the particular bus. ·
OPERATION OF CONTROL UNIT:
The control unit directs the information flow through ALU by:
- Selecting various Components in the system
- Selecting the Function of ALU Example: R1 <- R2 + R 1] MUX A selector (SELA): BUS A R [2] MUX B selector (SELB): BUS B R [3] ALU operation selector (OPR): ALU to ADD [4] Decoder destination selector (SELD): R1 Out Bus
Control Word
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Encoding of register selection fields
Encoding of ALU operations
Symbolic Designation Microoperation SELA SELB SELD OPR Control Word
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To remove the top item, the stack is popped by reading the memory word at address 3 and decrementing the content of SP. Item B is now on top of the stack since SP holds address
To insert a new item, the stack is pushed by incrementing SP and writing a word in the next-higher location in the stack. In a 64-word stack, the stack pointer contains 6 bits because 2^6 = 64.
Since SP has only six bits, it cannot exceed a number greater than 63 (111111 in binary). When 63 are incremented by 1, the result is 0 since 111111 + 1 = 1000000 in binary, but SP can accommodate only the six least significant bits. Similarly, when 000000 is decremented by 1, the result is 111111. The one-bit register FULL is set to 1 when the stack is full, and the one-bit register EMTY is set to 1 when the stack is empty of items.
DR is the data register that holds the binary data to be written into or read out of the stack.
PUSH:
If the stack is not full (FULL =0), a new item is inserted with a push operation. The push operation consists of the following sequences of microoperations:
SP ← SP + 1 Increment stack pointer M [SP] ← DR WRITE ITEM ON TOP OF THE STACK IF (SP = 0) then (FULL ← 1) Check is stack is full EMTY ← 0 Mark the stack not empty
The stack pointer is incremented so that it points to the address of next-higher word. A memory write operation inserts the word from DR into the top of the stack. SP holds the address of the top of the stack and that M[SP] denotes the memory word specified by the address presently available in SP. The first item stored in the stack is at address 1. The last item is stored at address 0. If SP reaches 0, the stack is full of items, so FULL is set to 1. This condition is reached if the top item prior to the last push was in location 63 and, after incrementing SP, the last item is stored in location 0. Once an item is stored in location 0, there are no more empty registers in the stack. If an item is written in the stack, obviously the stack cannot be empty, so EMTY is cleared to 0.
POP:
A new item is deleted from the stack if the stack is not empty (if EMTY = 0). The pop operation consists of the following sequences of microoperations:
DR ← M [SP] Read item on top of the stack SP ← SP - 1 Decrement stack pointer IF (SP = 0) then (EMTY ← 1) Check if stack is empty FULL ← 0 Mark the stack not full
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The top item is read from the stack into DR. The stack pointer is then decremented. If its value reaches zero, the stack is empty, so EMTY is set to 1.
This condition is reached if the item read was in location 1. Once this item is read out, SP is decremented and reaches the value 0, which is the initial value of SP. If a pop operation reads the item from location 0 and then SP is decremented, SP is changes to 111111, which is equivalent to decimal 63. In this configuration, the word in address 0 receives the last item in the stack. Note also that an erroneous operation will result if the stack is pushed when FULL = 1 or popped when EMTY = 1.
Memory Stack.
Figure 5.2: Computer memory with program, data, and stack segments
The implementation of a stack in the CPU is done by assigning a portion of memory to a stack operation and using a processor register as a stack pointer. Figure 5.2 shows a portion of computer memory partitioned into three segments: program, data, and stack. The program counter PC points at the address of the next instruction in the program which is used during the fetch phase to read an instruction.
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The three most common CPU organizations:
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ADDRESSING MODES :
- to give programming flexibility to the user
- to use the bits in the address field of the instruction efficiently
TYPES OF ADDRESSING MODES :
