MIPS - High Performance Computing - Lecture Slides, Slides of Computer Science

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High Performance Computing

Lecture 9

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MIPS 1 Function Call

void A() { … B(5); … } void B (int x) { int a, b; … return(); } ADDI R1, R0, 5 ADDI R29, R29, 4 SW 0(R29), R JAL B ADDI R29, R29, 4 SW 0(R29), R B : … 5 (int x) Return address Local int a Local int b ADDI R29, R29, 8 … SUBI R29, R29, 16 LW R31, 8(R29) JR R Function Call/Return Stack

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MIPS 1 Instruction Set

1. Conditional branch instructions

2. Floating point

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MIPS 1 Branch Instructions

What about a condition like R1 >= R You could use the BGEZ instruction Idea: Rewrite the condition as (R1 – R2) >= 0 SUB R3, R1, R2 / R3  R1 - R BGEZ R3, target / if R3 >= 0 goto target Problem: Possibility of overflow If R2 < 0, PC  PC + 4 - 16 BEQ, BNE, BLTZ R2, - 16 BGEZ, BLEZ, BLTZ, BGTZ Conditional Branch Mnemonics Example Meaning

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MIPS 1 Floating Point

 Assume that there is a separate floating point

register file

 32 32b floating point registers F0-F  A double (64b floating point value) occupies 2 registers  Even-odd pair, such as F0,F  Addressed as F

 Additional instructions

 Loads: LF (load float), LD (load double)  Arithmetic: ADDF (add float), ADDD (add double)

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Rationale for Separate FP Register File?

ALU FP Adder FP Multiplier 64 Registers 32 Integer Registers 32 FP Registers ALU FP Adder FP Multiplier

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Basic Computer Organization

Cache Main Memory I/O Bus I/O I/O MMU ALU Registers CPU Control

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Steps in Instruction Processing

1. Fetch instruction from Main Memory to CPU  Get instruction whose address is in PC from memory into IR  Increment PC
2. Decode the instruction  Understand instruction, addressing modes, etc  Calculate memory addresses and fetch operands
3. Execute the required operation  Do the required operation
4. Write the result of the instruction

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Timeline of events (CISC)

PC to memory Instruction in IR PC++; Decode Op1 address calculation Op1 fetched Op2 address calculation Op2 fetched Op done Write result Processor/Memory Speed disparity ~2 orders of magnitude

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Timeline of events (RISC)

PC to memory Instruction in IR PC++; Decode Op1 address calculation Op1 fetched Op2 fetched Op done Write result

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We will assume that …

1. Activity is overlapped in time where possible
   • PC increment and instruction fetch from memory?
   • Instruction decode and effective address calculation
2. Load-store ISA: the only instructions that take operands from memory are loads & stores
3. Main memory delays are not typically seen by the processor
   • Otherwise the timeline is dominated by them
   • There is some hardware mechanism through which most memory access requests can be satisfied at processor speeds (cache memory)